IS43DR16320B-25DBL ISSI, Integrated Silicon Solution Inc, IS43DR16320B-25DBL Datasheet - Page 6

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IS43DR16320B-25DBL

Manufacturer Part Number
IS43DR16320B-25DBL
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS43DR16320B-25DBL

Lead Free Status / Rohs Status
Compliant
IS43/46DR86400B, IS43/46DR16320B
Mode Register (MR) Diagram
Notes:
1.
2.
DDR2 Extended Mode Register 1 (EMR[1]) Setting
The extended mode register 1 stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and
additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be
written after power-up for proper operation. Extended mode register 1 is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1
and HIGH on BA0, and controlling pins A0 - A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to
writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete the write
operation to the extended mode register. Mode register contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used
for enabling reduced strength data-output driver. A3 - A5 determines the additive latency, A2 and A6 are used for ODT value
selection, A7 - A9 are used for OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
A13 is reserved for future use and must be set to 0 when programming the MR.
The minimum value for WR(write recovery for autoprecharge) is determined by tCK(Max) and maximum value for WR is determined by tCK(Min). WR in clock
cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode
register must be programmed to this value. This is also used with tRP to determine tDAL.
Address
A13
Field
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(1)
Register
Latency
Length
Mode
Burst
PD1
CAS
WR
DLL
TM
BT
0
0
0
A12
A11
A8
A6
A3
A2
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
A10
Active power down exit time
A5
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Slow exit(use tXARDS)
Fast exit (use tXARD)
Burst Type
Sequential
Interleave
DLL Reset
Yes
No
A9
A4
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WR(cycles)
BL
4
8
Reserved
Reserved
Reserved
2
3
4
5
6
CAS Latency
Reserved
Reserved
Reserved
Reserved
(2)
3
4
5
6
A7
0
1
Reserved
Normal
Mode
6

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