ADV7189BKSTZ Analog Devices Inc, ADV7189BKSTZ Datasheet
ADV7189BKSTZ
Specifications of ADV7189BKSTZ
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ADV7189BKSTZ Summary of contents
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FEATURES Multiformat video decoder supports NTSC-(J, M, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates three 54 MHz, Noise Shaped Video Clocked from a single 28 MHz crystal Line-locked clock-compatible (LLC) Adaptive-Digital-Line-Length-Tracking (ADLLT™), signal processing, and enhanced FIFO management gives mini- TBC functionality 5-line ...
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ADV7189B TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor ................................................... 4 Functional Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Electrical Characteristics............................................................. 6 Video Specifications..................................................................... 7 Timing Specifications .................................................................. 8 Analog Specifications................................................................... 8 Thermal Specifications ................................................................ ...
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C rystal Load Capacitor Value Selection................................... ypical Circuit Connection ........................................................... REVISION HISTORY 9/05—Rev Rev. B Changes to Table 1 ............................................................................6 Changes to Table 2 ............................................................................7 Changes to Table 3 and Table ...
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ADV7189B INTRODUCTION The ADV7189B is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced ...
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FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER Figure 1. Rev Page 5 of 104 ADV7189B ...
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... Digital I/O Supply Current PLL Supply Current Analog Supply Current Power-Down Current Power-Up Time 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ) MIN MAX 2 The min/max specifications are guaranteed over this range. 3 Pin 36 and Pin 79. 4 Pin 1, Pin 2, Pin 5 to Pin 8, Pin 12, Pin 17 to Pin 24, Pin 32 to Pin 35, Pin 73 to Pin 76, and Pin 80. ...
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... Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ). MIN MAX 2 The min/max specifications are guaranteed over this range VDD Symbol ...
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... Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ). MIN MAX 2 The min/max specifications are guaranteed over this range VDD Test Conditions ...
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... Parameter THERMAL CHARACTERISTICS Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) 1 Temperature range –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ) MIN MAX 2 The min/max specifications are guaranteed over this range. TIMING DIAGRAMS t 3 SDA SCLK OUTPUTS P0–P19, VS, P0– ...
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ADV7189B ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating A to GND 4 V VDD A to AGND 4 V VDD D to DGND 2.2 V VDD P to AGND 2.2 V VDD D to DGND 4 V VDDIO D to ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DGND 3 DVDDIO 4 P15 5 P14 6 P13 7 P12 8 DGND 9 DVDD 10 INTRQ 11 SFL DGND 14 DVDDIO P11 17 ...
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ADV7189B Table 7. Pin Function Descriptions Pin No. Mnemonic Type 3, 9, 14, 31, 71 DGND G 39, 40, 47, 53, AGND DVDDIO P 10, 30, 72 DVDD P 50 AVDD P 38 PVDD P 42, ...
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ANALOG FRONT END ANALOG INPUT MUXING The ADV7189B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder. F igure 6 outlines the overall structure of the input 1 ...
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ADV7189B SET INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION Table 8. Input Channel Switching Using INSEL[3:0] Description INSEL[3:0] Analog Input Pins 0000 CVBS1 = AIN1 (default) 0001 CVBS2 = AIN2 0010 CVBS3 = AIN3 0011 CVBS4 = AIN4 0100 CVBS5 = AIN5 ...
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Manual Input Muxing By accessing a set of manual override muxing registers, the analog input muxes of the ADV7189B can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, ...
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ADV7189B GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. POWER-SAVE MODES Power-Down PDBP, Address 0x0F[2] The digital core of the ADV7189B can be shut down by using a pin ( PWRDN ) and a ...
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GLOBAL PIN CONTROL Three-State Output Drivers TOD, Address 0x03[6] This bit allows the user to three-state the output drivers of the ADV7189B. Upon setting the TOD bit, the P[19:0], HS, VS, FIELD, and SFL pins are three-stated. The timing pins ...
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ADV7189B Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0x04[1] The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the ADV7189B core to an encoder in a decoder-encoder back-to-back arrangement. When EN_SFL_PIN is 0 (default), ...
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GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7189B. The other three registers contain status bits from the ADV7189B. IDENTIFICATION IDENT[7:0] Address 0x11[7:0] ...
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ADV7189B STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION LUMA DIGITIZED CVBS DIGITAL DIGITIZED Y (YC) FINE CLAMP CHROMA DIGITIZED CVBS DIGITAL CHROMA DIGITIZED C (YC) FINE DEMOD CLAMP RECOVERY A block diagram of the ADV7189B’s standard definition processor ...
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SYNC PROCESSING The ADV7189B extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches. The actual ...
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ADV7189B AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07[5] Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Setting AD_N443_EN to 1 (default) enables the detection. AD_P60_EN Enable Autodetection of PAL60, Address ...
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SRLS Select Raw Lock Signal, Address 0x51[6] Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits[1:0] in the Status 1 register). • The time_win signal is based on a line-to-line evaluation ...
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ADV7189B SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4[7:0] This register allows the user to control the gain of the Cr channel only. Table 24. SD_SAT_Cr Function SD_SAT_Cr[7:0] Description 0x80 (default) Chroma gain = 0 dB 0x00 Gain on Cb channel ...
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DEF_VAL_EN Default Value Enable, Address 0x0C[0] This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a stable ...
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ADV7189B 2 The following sections describe the I C signals that can be used to influence the behavior of the clamping block on the ADV7189B. CCLEN Current Clamp Enable, Address 0x14[4] The current clamp enable bit allows the user to ...
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An automatic mode for Y-shaped filtering is provided. In this mode, the ADV7189B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow ...
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ADV7189B Table 30. YSFM Function YSFM[4:0] Description 0'0000 Automatic selection including a wide-notch response (PAL/NTSC/SECAM) 0'0001 Automatic selection including a narrow-notch (default) response (PAL/NTSC/SECAM) 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 0'0111 ...
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COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS, Y RESAMPLE 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 12. Y S-VHS Combined Responses The filter plots in F igure 12 show the S-VHS 1 ...
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ADV7189B CSFM[2:0] C-Shaping Filter Mode, Address 0x17[7] The C-shaping filter mode bits allow the user to select from a range of low-pass filters, SH1 to SH5, and wideband mode for the chrominance signal. The auto-selection options automatically select from the ...
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Table 33. AGC Modes Input Video Type Luma Gain Any Manual gain luma. CVBS Dependent on horizontal sync depth. Peak White. Y/C Dependent on horizontal sync depth. Peak White. YPrPb Dependent on horizontal sync depth. Luma Gain LAGC[2:0] Luma Automatic ...
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ADV7189B For example, program the ADV7189B into manual fixed gain mode with a desired gain of 0.89: 1. Use Equation 1 to convert the gain: 0.89 × 2048 = 1822.72 2. Truncate to integer value: 1822.72 = 1822 3. Convert ...
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CG[11:0] Chroma Gain, Address 0x2D[3:0]; Address 0x2E[7:0]; CMG[11:0] Chroma Manual Gain, Address 0x2D[3:0]; Address 0x2E[7:0] Chroma Gain[11: dual-function register. If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] mode ...
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ADV7189B CHROMA TRANSIENT IMPROVEMENT (CTI) The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the ...
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DNR_TH[7:0] DNR Noise Threshold, Address 0x50[7:0] The DNR_TH[7:0] value is an unsigned 8-bit number used to determine the maximum edge that is interpreted as noise and therefore blanked from the luma data. Programming a large value into DNR_TH[7:0] causes the ...
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ADV7189B CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38[5:3] Table 46. CCMN Function CCMN[2:0] Description 0xx (default) Adaptive comb mode. 100 Disable chroma comb. 101 Fixed chroma comb (top lines of line memory). 110 Fixed chroma comb (all lines of line ...
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CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39[7:6] Table 49. CTAPSP Function CTAPSP[1:0] Description 00 Do not use. 01 PAL chroma comb adapts 5 lines (3 taps lines (2 taps); cancels cross luma only. 10 PAL chroma comb adapts ...
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ADV7189B AV CODE INSERTION AND CONTROLS 2 This section describes the I C-based controls that affect: • Insertion of AV codes into the data stream. • Data blanking during the vertical blank interval (VBI). • The range of data values ...
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BL_C_VBI Blank Chroma During VBI, Address 0x04[2] Setting BL_C_VBI high, the Cr and Cb values of all VBI lines are blanked. This is done so any data that may arrive during VBI is not decoded as color and output through ...
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ADV7189B SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only: • Beginning of HS signal via HSB[10:0] • End of HS signal via HSE[10:0] • Polarity of HS ...
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VS and FIELD Configuration The following controls allow the user to configure the behav- ior of the VS and FIELD output pins, as well as to generate embedded AV codes: • ADV encoder-compatible signals via NEWAVMODE • PVS, PF • ...
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ADV7189B 525 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 262 263 264 265 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 1 APPLIES IF NEMAVMODE = 0: MUST BE MANUALLY ...
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Table 56. Recommended User Settings for NTSC (See Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE5 0xE6 0xE7 NVBEGSIGN 1 ADVANCE BEGIN OF VSYNC BY NVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NVBEGDELO 1 0 ADDITIONAL DELAY ...
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ADV7189B 1 NVENDSIGN ADVANCE END OF VSYNC BY NVEND[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NVENDDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSEHO 1 0 ADVANCE BY 0.5 LINE VSYNC END Figure 24. NTSC Vsync End NVENDDELO ...
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Table 57. Recommended User Settings for PAL (See Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE8 0xE9 0xEA 622 623 624 625 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 310 311 312 313 OUTPUT VIDEO ...
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ADV7189B 622 623 624 625 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT 310 311 312 313 OUTPUT VIDEO HS OUTPUT VS OUTPUT FIELD OUTPUT Figure 27. PAL Typical Vsync/Field Positions Using Register Writes in 1 PVBEGSIGN ADVANCE BEGIN OF ...
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PVENDSIGN ADVANCE END OF VSYNC BY PVEND[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES PVENDDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSEHO 1 0 ADVANCE BY 0.5 LINE VSYNC END Figure 29. PAL Vsync End PVENDDELO PAL ...
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ADV7189B SYNC PROCESSING The ADV7189B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via 2 the following two I C bits. ENHSPLL Enable ...
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CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2[2] For certain video sources, the CRC data bits can have an invalid format. In such circumstances, the CRC checksum validation procedure can be disabled. The CGMSD bit goes high if the rising edge of ...
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ADV7189B CGMS Data Registers CGMS1[7:0], Address 0x96[7:0], CGMS2[7:0], Address 0x97[7:0], CGMS3[7:0], Address 0x98[7:0] F igure 33 shows the bit correspondence between the analog video waveform and the CGMS1/CGMS2/CGMS3 registers. CGMS3[7:4] are undetermined and should be masked ...
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Letterbox Detection Incoming video signals may conform to different aspect ratios (16:9 wide screen of 4:3 standard). For certain transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal WSS sequence is ...
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ADV7189B 2 The block is configured via the following ways: • GDECEL[15:0] allow data recovery on selected video lines on even fields to be enabled and disabled. • GDECOL[15:0] enable the data recovery on selected lines for ...
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Table 65. Data Byte Allocation Raw Information Bytes 2× Retrieved from the Video Line Gemstar Bit Names • DID. The data identification value is 0x140 (10-bit value). Care has been taken that ...
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ADV7189B Table 66. Gemstar 2× Data, Half-Byte Mode Byte D[9] D[ ...
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Table 69. Gemstar 1× Data, Full-Byte Mode Byte D[9] D[ ...
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ADV7189B NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0; the full-byte mode is enabled by CDECAD = 1. See the Gemstar Decode Ancillary Data Format, Address 0x4C[0] section. The data packet formats are shown in ...
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GDECEL[15:0] Gemstar Decoding Even Lines, Address 0x48[7:0]; Address 0x49[7:0] The 16 bits of the GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an even field. Setting ...
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ADV7189B Table 75. PAL Line Enable Bits and Corresponding Line Numbering Line Number Line[3:0] (ITU-R BT.470) Enable Bit 12 8 GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[ GDECOL[6] 3 ...
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Interrupt Request Output Operation When an interrupt event occurs, the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_DUR_SEL[1:0]. INTRQ_DURSEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[7:6] Table 76. INTRQ_DUR_SEL INTRQ_DURSEL[1:0] Description 00 (default) 3 Xtal periods ...
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ADV7189B PIXEL PORT CONFIGURATION The ADV7189B has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. T able 79 and T able 80 summarize the various functions that the 2 ...
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MPU PORT DESCRIPTION 2 The ADV7189B supports a 2-wire (I C-compatible) serial inter- face. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7189B and the system I master controller. Each slave device is recognized by ...
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ADV7189B REGISTER ACCESSES The MPU can write to or read from most of the ADV7189B’s registers, excepting the registers that are read-only or write- only. The subaddress register determines which register the next read or write operation accesses. All communications ...
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I C REGISTER MAPS Table 82. Common and Normal (Page 1) Register Map Details Register Name Input Control Video Selection Reserved Output Control Extended Output Control Reserved Reserved Autodetect Enable Contrast Reserved Brightness Hue Default Value Y Default Value ...
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ADV7189B Register Name Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 GemStar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free Run ...
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Register Name Drive Strength Reserved IF Comp Control VS Mode Control Table 83. Common and Normal (Page 1) Register Map Bit Names Register Name Bit 7 Bit 6 Input Control VID_SEL.3 VID_SEL.2 Video Selection ENHSPLL Reserved Output Control VBI_EN TOD ...
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ADV7189B Register Name Bit 7 Bit 6 Vsync Field VSBHO VSBHE Control 2 Vsync Field VSEHO VSEHE Control 3 Hsync Position HSB.10 Control 1 Hsync Position HSB.7 HSB.6 Control 2 Hsync Position HSE.7 HSE.6 Control 3 Polarity PHS NTSC Comb ...
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Register Name Bit 7 Bit 6 SD Offset Cb SD_OFF_CB.7 SD_OFF_CB.6 SD Offset Cr SD_OFF_CR.7 SD_OFF_CR.6 SD Saturation SD_SAT_CB.7 SD_SAT_CB Saturation SD_SAT_CR.7 SD_SAT_CR.6 Cr NTSC V Bit NVBEGDEL O NVBEGDEL E Begin NTSC V Bit End NVENDDEL O ...
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ADV7189B INTERRUPT REGISTER MAP The following registers are located in Register Access Page 2. Table 85. Interrupt (Page 2) Register Map Details Subaddress Register Bit Description 0x40 Interrupt INTRQ_OP_SEL[1:0]. Config 1 Interrupt Drive Level Select Register Access ...
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Subaddress Register Bit Description 0x44 Interrupt SD_LOCK_MSKB Mask 1 SD_UNLOCK_MSKB Read/Write Register Reserved Reserved Register Reserved Access Page 2 SD_FR_CHNG_MSKB MV_PS_CS_MSKB Reserved 0x45 Reserved 0x46 Interrupt CCAPD_Q Status 2 Read-Only Register GEMD_Q Register Access Page 2 CGMS_CHNGD_Q WSS_CHNGD_Q Reserved Reserved ...
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ADV7189B Subaddress Register Bit Description 0x48 Interrupt CCAPD_MSKB Mask 2 GEMD_MSKB Read/ Write CGMS_CHNGD_MSKB Register WSS_CHNGD_MSKB Access Page 2 Reserved Reserved Reserved MPU_STIM_INTRQ_MSKB 0x49 Raw Status SD_OP_50Hz 3 SD 60/50Hz frame rate at output Read Only SD_V_LOCK Register Register Access ...
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Subaddress Register Bit Description 0x4B Interrupt SD_OP_CHNG_CLR Clear 3 SD_V_LOCK_CHNG_CLR Write Only Register SD_H_LOCK_CHNG_CLR Register SD_AD_CHNG_CLR Access Page 2 SCM_LOCK_CHNG_CLR PAL_SW_LK_CHNG_CLR Reserved Reserved 0x4C Interrupt SD_OP_CHNG_MSKB Mask 2 SD_V_LOCK_CHNG_ MSKB Read / Write Register SD_H_LOCK_CHNG_ MSKB Register Access SD_AD_CHNG_ MSKB ...
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ADV7189B The following registers are located in the Common I Table 86. Common and Normal (Page 1) Register Map Details Subaddress Register Bit Description 0x00 Input INSEL[3:0]. The INSEL bits allow the Control user to select an input channel as ...
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Subaddress Register Bit Description 0x01 Video Reserved Selection ENVSPROC Reserved BETACAM ENHSPLL Reserved 0x03 Output SD_DUP_AV. Duplicates the AV Control codes from the luma into the chroma path. Reserved OF_SEL[3:0]. Allows the user to choose from a set of output ...
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ADV7189B Subaddress Register Bit Description 0x07 Autodetect AD_PAL_EN. PAL B/G/I/H Enable autodetect enable. AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL 60 autodetect enable. AD_N443_EN. NTSC443 autodetect enable. AD_SECAM_EN. SECAM autodetect enable. ...
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Subaddress Register Bit Description 0x0F Power Reserved Management PDBP. Power-down bit priority selects between PWRDN bit or PIN. Reserved PWRDN. Power down places the decoder in a full power-down mode. Reserved RES. Chip reset loads all I with default values. ...
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ADV7189B Subaddress Register Bit Description 0x15 Digital Reserved Clamp DCT[1:0]. Digital clamp timing Control 1 determines the time constant of the digital fine clamp circuitry. Reserved 0x17 Shaping YSFM[4:0]. Selects Y-Shaping Filter Filter mode when in CVBS only mode. Control ...
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Subaddress Register Bit Description 0x18 Shaping WYSFM[4:0]. Wideband Y-Shaping Filter Filter mode allows the user to Control 2 select which Y-shaping filter is used for the Y component of Y/C, YPbPr, B/W input signals also used when a ...
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ADV7189B Subaddress Register Bit Description 0x27 Pixel Delay LTA[1:0]. Luma timing adjust allows Control the user to specify a timing difference between chroma and luma samples. Reserved CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and ...
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Subaddress Register Bit Description 0x2D Chroma CMG[11:8]. Chroma manual gain Gain can be used to program a desired Control 1 manual chroma gain. Reading back from this register in AGC mode gives the current gain. Reserved CAGT[1:0]. Chroma automatic gain ...
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ADV7189B Subaddress Register Bit Description 0x34 HS Position HSE[10:8]. HS end allows the Control 1 positioning of the HS output within the video line. Reserved HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved ...
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Subaddress Register Bit Description 0x38 NTSC YCMN[2:0]. luma Comb comb mode, NTSC. Control CCMN[2:0]. chroma comb mode, NTSC. CTAPSN[1:0]. chroma comb taps, NTSC. Bits Comments Adaptive 3-line, 3-tap luma ...
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ADV7189B Subaddress Register Bit Description 0x39 PAL Comb YCMP[2:0]. luma comb mode, PAL. Control CCMP[2:0]. chroma comb mode, PAL. CTAPSP[1:0]. chroma comb taps, PAL. 0x3A Reserved PWRDN_ADC_2. Enables power- down of ADC2. PWRDN_ADC_1. Enables power- down of ADC1. PWRDN_ADC_0. Enables ...
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Subaddress Register Bit Description 0x41 Resample Reserved Control SFL_INV. Controls the behavior of the PAL switch bit. Reserved. 0x48 Gemstar GDECEL[15:8]. See the Comments Control 1 column. 0x49 Gemstar GDECEL[7:0]. See the Comments Control 2 column 0x4A Gemstar GDECOL[15:8]. See ...
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ADV7189B Subaddress Register Bit Description 0x51 Lock Count CIL[2:0]. Count-into-lock determines the number of lines the system must remain in lock before showing a locked status. COL[2:0]. Count-out-of-lock determines the number of lines the system must remain out-of-lock before showing ...
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Subaddress Register Bit Description 0x99 CCAP1 CCAP1[7:0] (Read Only) Closed caption data register. 0x9A CCAP2 CCAP2[7:0] (Read Only) Closed caption data register. 0x9B Letterbox 1 LB_LCT[7:0] (Read Only) Letterbox data register. 0x9C Letterbox 2 LB_LCM[7:0] (Read Only) Letterbox data register. ...
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ADV7189B Subaddress Register Bit Description 0xC4 ADC ADC2_SW[3:0]. Manual muxing SWITCH 2 control for ADC2. Reserved ADC_SW_MAN_EN. Enable manual setting of the input signal muxing. 0xDC Letterbox LB_TH[4:0]. Sets the threshold Control 1 value that determines if a line is ...
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Subaddress Register Bit Description 0xE5 NTSC V Bit NVBEG[4:0]. How many lines after Begin l rollover to set V high. COUNT NVBEGSIGN NVBEGDELE. Delay V bit going high by one line relative to NVBEG (even field). NVBEGDELO. Delay V bit ...
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ADV7189B Subaddress Register Bit Description 0xE9 PAL V Bit PVEND[4:0]. How many lines after End l rollover to set V low. COUNT PVENDSIGN PVENDDELE. Delay V bit going low by one line relative to PVEND (even field). PVENDDELO. Delay V ...
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Subaddress Register Bit Description 0xF9 VS Mode EXTEND_VS_MAX_FREQ Control EXTEND_VS_MIN_FREQ VS_COAST_MODE[1:0] Reserved Bits Comments 0 Limit maximum Vsync frequency to 66.25 Hz (475 lines/frame) 1 Limit maximum Vsync frequency to 70.09 Hz ...
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ADV7189B PROGRAMMING EXAMPLES EXAMPLES USING 28 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN5) All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10. Table 87. Mode 1 CVBS Input ...
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Mode 2 S-Video Input (Y on AIN1 and C on AIN4) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10. Table 88. Mode 2 S-Video Input Register Address Register Value 0x00 0x06 0x03 0x00 0x15 ...
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ADV7189B Mode 3 YPrPb Input 525i/625i (Y on AIN2 AIN3, and Pb on AIN6) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10. Table 89. Mode 3 YPrPb Input 525i/625i Register Address Register ...
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Mode 4 CVBS Tuner Input PAL Only on AIN4 10-bit, ITU-R BT.656 output on P19 to P10. Table 90. Mode 4 CVBS Tuner Input PAL Only Register Address Register Value 0x00 0x83 0x03 0x00 0x07 0x01 0x15 0x00 0x17 0x41 ...
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ADV7189B EXAMPLES USING 27 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN5) All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10. Table 91. Mode 1 CVBS Input Register Address Register Value 0x00 ...
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Mode 2 S-Video Input (Y on AIN1 and C on AIN4) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10. Table 92. Mode 2 S-Video Input Register Address Register Value 0x00 0x06 0x03 0x00 0x15 ...
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ADV7189B Mode 4 CVBS Tuner Input PAL Only on AIN4 10-bit, ITU-R BT.656 output on P19 to P10. Table 94. Mode 4 CVBS Tuner Input PAL Only Register Address Register Value 0x00 0x83 0x03 0x00 0x07 0x01 0x15 0x00 0x17 ...
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PCB LAYOUT RECOMMENDATIONS The ADV7189B is a high precision, high speed, mixed-signal device. To achieve the maximum performance from the part important to have a well laid out PCB board. The following is a guide for designing a ...
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ADV7189B DIGITAL INPUTS The digital inputs on the ADV7189B are designed to work with 3.3 V signals, and are not tolerant signals. Extra compo- nents are needed logic signals are required to be applied ...
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TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7189B video decoder are shown in the ADV7189B, refer to the ADV7189B evaluation note. IN Figure 45. ADI Recommended Anti-Aliasing Circuit for All Input Channels F igure 45 and 2 6 ...
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ADV7189B DVDDIO AGND DGND S-VIDEO ANTIALIAS FILTER CIRCUIT ANTIALIAS Y FILTER CIRCUIT ANTIALIAS Pr FILTER CIRCUIT ANTIALIAS Pb FILTER CIRCUIT ANTIALIAS CBVS FILTER CIRCUIT RECOMMENDED ANTIALIAS FILTER CIRCUIT IS SHOWN IN FIGURE 45 ON THE PREVIOUS PAGE. THIS CIRCUIT INCLUDES ...
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... PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1 Model Temperature Range ADV7189BKSTZ 0°C to +70° ADV7189BBSTZ –40°C to +85° EVAL-ADV7189BEB 1 The ADV7189B is a Pb-free, environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface-mount soldering 255° ...
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ADV7189B NOTES Rev Page 102 of 104 ...
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NOTES Rev Page 103 of 104 ADV7189B ...
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ADV7189B NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, ...