ADV7184BSTZ Analog Devices Inc, ADV7184BSTZ Datasheet
ADV7184BSTZ
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ADV7184BSTZ Summary of contents
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FEATURES Multiformat video decoder supports NTSC (J/M/4.43), PAL (B/D/G/H/I/M/N), SECAM Integrates four 54 MHz, 10-bit ADCs SCART fast blank support Clocked from a single 28.63636 MHz crystal Line-locked clock-compatible (LLC) Adaptive Digital Line Length Tracking (ADLLT™), signal processing, and enhanced ...
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ADV7184 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor (SDP)........................................ 4 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Electrical Characteristics............................................................. 5 ...
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User Sub Map...............................................................................99 PCB Layout Recommendations ................................................. 109 Analog Interface Inputs........................................................... 109 Power Supply Decoupling ....................................................... 109 PLL ............................................................................................. 109 Digital Outputs (Both Data and Clocks) .............................. 109 REVISION HISTORY 2/07—Rev Rev. A Corrected Register and Bit Names................................... ...
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ADV7184 INTRODUCTION The ADV7184 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-video, and component video into a digital ITU-R BT.656 format. The advanced, ...
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SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD VDD Operating temperature range, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential ...
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ADV7184 VIDEO SPECIFICATIONS VDD VDD otherwise noted). Table Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted ...
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THERMAL SPECIFICATIONS Table 4. Parameter Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) TIMING SPECIFICATIONS VDD VDD otherwise noted). Table Parameter Symbol ...
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ADV7184 TIMING DIAGRAMS t SDA SCLK OUTPUTS P0 TO P15, VS P15, HS, VS, FIELD Figure Timing t 9 OUTPUT LLC1 t 11 ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating A to AGND 4 V VDD D to DGND 2.2 V VDD P to AGND 2.2 V VDD D to DGND 4 V VDDIO −0 +0.3 V VDDIO ...
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ADV7184 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DGND 3 DVDDIO 4 P11 5 P10 DGND 9 DVDD 10 INT 11 SFL 12 TEST2 13 DGND 14 DVDDIO 15 TEST8 16 TEST12 17 ...
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Pin No. Mnemonic Type 67 SDA I/O 68 SCLK I 66 ALSB I 64 RESET I 27 LLC1 O 26 LLC2 O 29 XTAL I 28 XTAL1 O 36 PWRDN ELPF I 12 SFL O ...
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ADV7184 ANALOG FRONT END ADC_SW_MAN_EN AIN1 AIN7 AIN2 1 AIN8 AIN3 0 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN3 1 AIN9 AIN4 0 AIN10 AIN5 AIN11 AIN6 AIN12 AIN2 1 AIN8 AIN5 0 AIN11 AIN6 AIN12 AIN4 1 AIN4 ...
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ANALOG INPUT MUXING The ADV7184 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder. Figure 6 outlines the overall structure of the input muxing provided in the ADV7184. As can ...
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ADV7184 INSEL [3:0], Input Selection, Address 0x00 [3:0] The INSEL bits allow the user to select the input channel and format. Depending on the PCB connections, only a subset of the INSEL modes is valid. INSEL [3:0] not only switches ...
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Table 10. Input Channel Assignments Input Channel Pin No. AIN7 41 CVBS7 AIN1 42 CVBS1 AIN8 43 CVBS8 AIN2 44 CVBS2 AIN9 45 CVBS9 AIN3 46 CVBS3 AIN10 57 CVBS10 AIN4 58 CVBS4 AIN11 59 CVBS11 AIN5 60 CVBS5 AIN12 ...
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ADV7184 ADC_SW_MAN_EN, Manual Input Muxing Enable, Address 0xC4 [7] ADC0_SW [3:0], ADC0 Mux Configuration, Address 0xC3 [3:0] ADC1_SW [3:0], ADC1 Mux Configuration, Address 0xC3 [7:4] ADC2_SW [3:0], ADC2 Mux Configuration, Address 0xC4 [3:0] ADC3_SW [3:0], ADC3 Mux Configuration, Address 0xF3 ...
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The alpha blend factor is selected with the I MAN_ALPHA_VAL [6:0]. Overlay is not possible in fixed alpha blending mode. • Dynamic Switching (Fast Mux). The FB pin can be used to select the source. This enables dynamic multiplexing between ...
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ADV7184 FAST BLANK (FB PIN) CVBS ADC0 Fast Blank Edge Shaping FB_EDGE_SHAPE [2:0], Address 0xEF [2:0] To improve the picture transition for high speed fast blank switching, an edge-shaping mode is available on the ADV7184. Depending on ...
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Fast Blank and Contrast Reduction Programmable Thresholds The internal fast blank and contrast reduction signals are resolved from the trilevel FB signal using two comparators, as shown in Figure 11. To facilitate compliance with different input level standards, the reference ...
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ADV7184 FB_INV, Address 0xED [3], Write Only The interpretation of the polarity of the signal applied to the FB pin can be changed using FB_INV. 0 (default)—The fast blank pin is active high. 1—The fast blank pin is active low. ...
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GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. POWER-SAVING MODES Power-Down PDBP, Address 0x0F [2] The digital core of the ADV7184 can be shut down by using the PWRDN pin or the PWRDN bit. ...
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ADV7184 strength controls are provided by the DR_STR_S, DR_STR_C, and DR_STR bits of Register 0xF4. 0 (default)—The output drivers are enabled. 1—The output drivers are three-stated. Three-State LLC Drivers TRI_LLC, Address 0x1D [7] This bit allows the output drivers for ...
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GLOBAL STATUS REGISTERS Three registers provide summary information about the video decoder: Status Register 1, Status Register 2, and Status Register 3. These registers contain status bits that report operational information to the user. Status Register 1 [7:0], Address 0x10 ...
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ADV7184 STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION LUMA DIGITIZED CVBS DIGITAL DIGITIZED Y (YC) FINE CLAMP CHROMA DIGITIZED CVBS DIGITAL CHROMA DIGITIZED C (YC) FINE CLAMP RECOVERY A block diagram of the ADV7184 standard definition processor (SDP) ...
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SYNC PROCESSING The ADV7184 extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction is optimized to support imperfect video sources, such as videocassette recorders with head switches. The actual ...
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ADV7184 AD_SEC525_EN, SECAM 525 Autodetect Enable, Address 0x07 [7] 0 (default)—Disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component. 1—Enables autodetection. AD_SECAM_EN, SECAM Autodetect Enable, Address 0x07 [6] 0—Disables the autodetection of SECAM. 1 (default)—Enables ...
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Lock-Related Controls Lock information is presented to the user through Bits [1:0] of Status Register 1. See the Status Register 1 [7:0], Address 0x10 [7:0] section. Figure 13 outlines the signal flow and the controls that are available to influence ...
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ADV7184 FSCLE, F Lock Enable, Address 0x51 [7] SC The FSCLE bit allows the user to choose if the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits ...
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SD_OFF_CB [7:0], SD Offset Cb Channel, Address 0xE1 [7:0] These bits allow the user to adjust the hue of the picture by selecting the offset for the Cb channel. There is a functional overlap with the HUE [7:0] bits. Table ...
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ADV7184 DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1] This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7184 cannot lock to the video signal. 0—Disables free-run mode. If the decoder is ...
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DCT [1:0], Digital Clamp Timing, Address 0x15 [6:5] The clamp timing register determines the time constant of the digital fine-current clamp circuitry important to realize that the digital fine-current clamp reacts quickly, correcting any residual dc level error ...
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ADV7184 In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (because they can successfully be combed) and for luma components of YPrPb and Y/C sources (because they need not be combed). For poor quality signals, ...
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WYSFMOVR, Wideband Y-Shaping Filter Override, Address 0x18 [7] Setting the WYSFMOVR bit enables the use of the WYSFM [4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma-shaping filters in the Y-Shaping ...
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ADV7184 COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, Y RESAMPLE 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 19. Y NTSC Notch Filter Responses CHROMA FILTER Data from the digital fine-clamp block is ...
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GAIN OPERATION The gain control within the ADV7184 is done on a purely digital basis. The input ADCs support a 10-bit range, mapped into a 1.6 V analog voltage range. Gain correction takes place after the digitization in the form ...
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ADV7184 Luma Gain LAGC [2:0], Luma Automatic Gain Control, Address 0x2C [6:4] The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path. Analog Devices internal parameters can be used to ...
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BETACAM, Enable BETACAM Levels, Address 0x01 [5] If YPrPb data is routed through the ADV7184, the automatic gain control modes can target different video input levels, as outlined in Table 44. Note that the BETACAM bit is valid only if ...
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ADV7184 Chroma Gain CAGC [1:0], Chroma Automatic Gain Control, Address 0x2C [1:0] These two bits select the basic mode of operation for automatic gain control in the chroma path. Table 45. CAGC [1:0] Function CAGC [1:0] Description 00 Manual fixed ...
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CHROMA TRANSIENT IMPROVEMENT (CTI) The signal bandwidth allocated for chroma is typically much smaller than that of luminance. With older devices, this was a valid way to fit a color video signal into a given overall band- width because the ...
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ADV7184 DNR_EN, Digital Noise Reduction Enable, Address 0x4D [5] 0—Bypasses DNR (disables it). 1 (default)—Enables DNR on the luma data. DNR_TH [7:0], DNR NoiseThreshold, Address 0x50 [7:0] The DNR1 block is positioned before the luma peaking block. The DNR_TH [7:0] ...
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CCMN [2:0], Chroma Comb Mode NTSC, Address 0x38 [5:3] Table 52. CCMN [1:0] Function CCMN [2:0] Description 000 (default) Adaptive comb mode 100 Disable chroma comb 101 Fixed chroma comb (top lines of line memory) 110 Fixed chroma comb (all ...
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ADV7184 PAL Comb Filter Settings Used for PAL B/G/H/I/D, PAL M, PAL Combinational N, PAL 60, and NTSC 4.43 CVBS inputs. PSFSEL [1:0], Split Filter Selection PAL, Address 0x19 [1:0] PFSEL [1:0] selects how much of the overall signal bandwidth ...
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Vertical Blank Control Each vertical blank control register (Addresses 0xEB and 0xEC) has the same meaning for the following bit settings: 00—Early by one line. 10—Delayed by one line. 11—Delayed by two lines. 01 (default)—Described in each register section. NVBIOLCM ...
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ADV7184 In a 16-bit output interface where Y and Cr/Cb are delivered via separate data buses, the AV code is over the whole 16 bits. The SD_DUP_AV bit allows the user to replicate the AV codes on both buses; therefore, ...
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RANGE, Range Selection, Address 0x04 [0] AV codes (as per ITU-R BT.656, formerly known as CCIR 656) consist of a fixed header made up of 0xFF and 0x00 values. These two values are reserved and therefore are not to be ...
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ADV7184 Table 61. HS Timing Parameters (see Figure 26) HS Begin Adjust Standard (HSB [10:0]) (Default) NTSC 00000000010 NTSC Square 00000000010 Pixel PAL 00000000010 LLC1 PIXEL BUS ACTIVE EAV VIDEO HS HSE[10:0] 4 ...
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NEWAVMODE, New AV Mode, Address 0x31 [4] 0—EAV/SAV codes are generated to suit Analog Devices encoders. No adjustments are possible. 1 (default)—Enables the manual position of VS/FIELD and AV codes using Register 0x32, Register 0x33, and Register 0xE5 to Register ...
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ADV7184 525 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 262 263 264 265 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 F NFTOG[4:0] = 0x3 *APPLIES IF NEMAVMODE = 0: MUST BE MANUALLY SHIFTED ...
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NVBEGSIGN ADVANCE BEGIN OF VSYNC BY NVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES NVBEGDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSBHO 1 0 ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 29. NTSC Vsync Begin NVBEGDELO, NTSC ...
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ADV7184 For all NTSC/PAL vsync timing controls, both the V bit in the AV code and the vsync on the VS pin are modified. NFTOGDELO, NTSC Field Toggle Delay on Odd Field, Address 0xE7 [7] 0 (default)—No delay. 1—Delays the ...
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OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 310 311 312 313 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 F PFTOG[4:0] = 0x3 Figure 32. PAL Default (ITU-R BT.656), the Polarities of HS, ...
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ADV7184 1 PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? YES PVBEGDELO 1 0 ADDITIONAL DELAY BY 1 LINE VSBHO 1 0 ADVANCE BY 0.5 LINE VSYNC BEGIN Figure 34. PAL Vsync Begin PVENDDELO, ...
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PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5] 0—Delays the field transition. Set for manual programming. 1 (default)—Advances the field transition. Not recommended for user programming. PFTOG, PAL Field Toggle, Address 0xEA [4:0] The default value of PFTOG is 00011, ...
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ADV7184 VDP Manual Configuration MAN_LINE_PGM, Enable Manual Line Programming of VBI Standards, Address 0x64 [7], User Sub Map The user can configure the VDP to decode different standards on a line-to-line basis through manual line programming. For this, the user ...
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Table 67. VBI Data Standards for Manual Configuration VBI_DATA_Px_Ny PAL—625/50 0000 Disable VDP 0001 Teletext system identified by VDP_TTXT_TYPE 0010 VPS—ETSI EN 300 231 V 1.3.1 0011 VITC 0100 WSS ITU-R BT.1119-1/ETSI.EN.300294 0101 Reserved 0110 Reserved 0111 CC 1000 to ...
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ADV7184 VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual Selection of Teletext Type, Address 0x60 [2], User Sub Map 0 (default)—Manual programming of the teletext type is disabled. 1—Manual programming of the teletext type is enabled. VDP_TTXT_TYPE_MAN [1:0], Specify the Teletext Type, Address 0x60 [1:0], ...
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The checksum value equal to the nine LSBs of the sum of the nine LSBs of the DID, SDID, and dc, as well as all UDWs in the packet. Prior to the start of the ...
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ADV7184 Table 72. Ancillary Data in Byte Output Format Byte padding ...
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Table 74. Framing Code Sequence for Different VBI Standards VBI Standard Length in Bits TTXT_SYSTEM_A (PAL) 8 TTXT_SYSTEM_B (PAL) 8 TTXT_SYSTEM_B (NTSC) 8 TTXT_SYSTEM_C (PAL and NTSC) 8 TTXT_SYSTEM_D (PAL and NTSC) 8 VPS (PAL) 16 VITC (NTSC and PAL) ...
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ADV7184 INTERFACE 2 Dedicated I C readback registers are available for CC, CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a high data rate standard, data extraction is supported only through the ancillary data packet. ...
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VDP—Interrupt-Based Reading of VDP I Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the AVAILABLE status bit. The user can configure the video decoder to trigger an ...
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ADV7184 VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2], User Sub Map 1—Clears the VDP_CGMS_WSS_CHNGD_Q bit. VDP_GS_VPS_PDC_UTC_CHNG_CLR, Address 0x4F [4], User Sub Map 1—Clears the VDP_GS_VPS_PDC_UTC_CHNG_Q bit. VDP_VITC_CLR, Address 0x4F [6], User Sub Map 1—Clears the VDP_VITC_Q bit. STANDARD DETECTION AND IDENTIFICATION The standard ...
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STDI Readback Values for SD, PR, and HD The readback values provided are only valid when using a crystal with the recommended 28.63636 MHz frequency. Table 76. STDI Results for Video Standards (SD, PR, and HD) Video Standard BL [13:0] ...
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ADV7184 READBACK REGISTERS Teletext Because teletext is a high data rate standard, the decoded bytes are available only as ancillary data. However, a TTXT_AVL bit 2 is provided that the user can check ...
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CGMS and WSS The CGMS and WSS data packets convey the same type of information for different video standards. WSS is for PAL and CGMS is for NTSC; therefore, the CGMS and WSS readback registers are shared. WSS is biphase ...
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ADV7184 SEQUENCE 11.0µs +100 IRE +70 IRE 0 IRE –40 IRE 11.2µs 10.5 ± 0.25µs 50 IRE 40 IRE REFERENCE COLOR BURST FREQUENCY = F AMPLITUDE = 40 IRE 1 Table 79. CGMS Readback Registers Signal Name CGMS_WSS_DATA_0 [3:0] CGMS_WSS_DATA_1 ...
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VITC VITC has a sequence of 10 syncs in between each data byte. The VDP strips these syncs from the data stream to output only the data bytes. The VITC results are available in the VDP_VITC_DATA_0 to VDP_VITC_DATA_8 registers (Register ...
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ADV7184 VPS/PDC/UTC/Gemstar The readback registers for VPS, PDC, and UTC are shared. Gemstar is a high data rate standard and therefore is available only through the ancillary stream. For evaluation purposes, any one line of Gemstar is available through the ...
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Table 83. GS/VPS/PDC/UTC Readback Registers Signal Name GS_VPS_PDC_UTC_BYTE_0 [7:0] GS_VPS_PDC_UTC_BYTE_1 [7:0] GS_VPS_PDC_UTC_BYTE_2 [7:0] GS_VPS_PDC_UTC_BYTE_3 [7:0] VPS_PDC_UTC_BYTE_4 [7:0] VPS_PDC_UTC_BYTE_5 [7:0] VPS_PDC_UTC_BYTE_6 [7:0] VPS_PDC_UTC_BYTE_7 [7:0] VPS_PDC_UTC_BYTE_8 [7:0] VPS_PDC_UTC_BYTE_9 [7:0] VPS_PDC_UTC_BYTE_10 [7:0] VPS_PDC_UTC_BYTE_11 [7:0] VPS_PDC_UTC_BYTE_12 [7:0] 1 The register is a readback register; ...
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ADV7184 The format of the data packet depends on the following criteria: • Transmission is Gemstar 1× or Gemstar 2×. • Data is output in 8-bit or 4-bit format (see the GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0] ...
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Table 85. Data Byte Allocation Raw Information Bytes Gemstar 2× Retrieved from the Video Line Gemstar Bit Names • DID. The data identification value is 0x140 (10-bit value). Care has been taken ...
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ADV7184 Table 86. Gemstar 2× Data, Half-Byte Mode Byte D [9] D [ ...
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Table 89. Gemstar 1× Data, Full-Byte Mode Byte D [9] D [ ...
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ADV7184 Table 92. PAL CC Data, Half-Byte Mode Byte D [9] D [ ...
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To retrieve closed caption data services on PAL (Line 335), GDECEL [14] must be set. The default value of GDECEL [15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CC data from any line ...
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ADV7184 GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0] The 16 bits of the GDECOL [15:0] form a collection of 16 indi- vidual line decode enable signals. See Table 94 and Table 95. To retrieve closed ...
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LB_TH [4:0], Letterbox Threshold Control, Address 0xDC [4:0] Table 97. LB_TH [4:0] Function LB_TH [4:0] Description 01100 Default threshold for detection of black lines (default) 01101 to Increase threshold (need larger active video 10000 content before identifying nonblack lines) 00000 ...
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ADV7184 Interrupt Request Output Operation When an interrupt event occurs, the interrupt pin INTRQ goes low, with a programmable duration given by INTRQ_DUR_SEL [1:0] INTRQ_DUR_SEL [1:0], Interrupt Duration Select, Address 0x40 [7:6], User Sub Map Table 98. INTRQ_DUR_SEL [1:0] Function ...
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PIXEL PORT CONFIGURATION The ADV7184 has a very flexible pixel port that can be config- ured in a variety of formats to accommodate downstream ICs. Table 101 and Table 102 summarize the various functions that the ADV7184 pins can have ...
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ADV7184 MPU PORT DESCRIPTION 2 The ADV7184 supports a 2-wire (I C-compatible) serial inter- face. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7184 and the system I master controller. Each slave device is recognized ...
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REGISTER ACCESSES The MPU can write to and read from all of the ADV7184 registers except those that are read only or write only. The subaddress register determines which register the next read or write operation accesses. All communications with ...
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ADV7184 REGISTER MAPS USER MAP The collective name for the registers in Table 104 is the user map. Table 104. User Map Register Details Address Dec Hex Register Name Input Control RW VID_SEL.3 ...
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Address Dec Hex Register Name Gemstar Control 1 RW GDECEL. Gemstar Control 2 RW GDECEL Gemstar Control 3 RW GDECOL. Gemstar Control 4 RW GDECOL Gemstar Control 5 ...
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ADV7184 Table 105 provides a detailed description of the registers located in the user map. Table 105. User Map Detailed Description Address Register Bit Description 0x00 Input Control INSEL [3:0]. These bits allow the user to select an input channel ...
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Address Register Bit Description 0x03 Output Control SD_DUP_AV. This bit duplicates the AV codes from the luma into the chroma path. Reserved. OF_SEL [3:0]. These bits allow the user to choose from a set of output formats. TOD. Three-state output ...
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ADV7184 Address Register Bit Description 0x0A Brightness Register BRI [7:0]. These bits control the brightness of the video signal. 0x0B Hue Register HUE [7:0]. These bits contain the value for the color hue adjustment. 0x0C Default Value Y DEF_VAL_EN. Default ...
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Address Register Bit Description FREE_RUN_ACT. STD_FLD_LEN. INTERLACED. PAL_SW_LOCK. Analog Control Reserved. Internal (Write Only) XTAL_TTL_SEL. Reserved. 0x14 Analog Clamp Reserved. Control CCLEN. Current clamp enable. This bit allows the user to switch off the current sources in the analog front ...
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ADV7184 Address Register Bit Description CSFM [2:0]. C-shaping filter mode. These bits allow selection from a range of low- pass chrominance filters, SH1to SH5, and wideband mode. 0x18 Shaping Filter WYSFM [4:0]. Wideband Y-shaping filter Control 2 mode. These bits ...
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Address Register Bit Description CTA [2:0]. Chroma timing adjust. These bits allow a specified timing difference between the luma and chroma samples. AUTO_PDC_EN. This bit automatically programs the LTA/CTA values to align luma and chroma at the output for all ...
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ADV7184 Address Register Bit Description 0x31 Vsync Field Reserved. Control 1 HVSTIM. This bit selects where within a line of video the VS signal is asserted. NEWAVMODE. Sets the EAV/SAV mode. Reserved. 0x32 Vsync Field Reserved. Control 2 VSBHE. VSBHO. ...
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Address Register Bit Description CCMN [2:0]. Chroma comb mode NTSC. CTAPSN [1:0]. Chroma comb taps NTSC. 0x39 PAL Comb Control YCMP [2:0]. Luma comb mode PAL. CCMP [2:0]. Chroma comb mode PAL. CTAPSP [1:0]. Chroma comb taps PAL. 0x3A ADC ...
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ADV7184 Address Register Bit Description 0x41 Resample Control Reserved. SFL_INV. This bit controls the behavior of the PAL switch bit. Reserved. 0x48 Gemstar Control 1 GDECEL [15:8]. See the Comments column. 0x49 Gemstar Control 2 GDECEL [7:0]. See the Comments ...
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Address Register Bit Description 0x69 Configuration 1 SDM_SEL [1:0]. Y/C and CVBS autodetect mode select. Reserved. 0x86 STDI Control Reserved. STDI_LINE_COUNT_MODE. Reserved. 0x8F Free-Run Line Reserved. Length 1 LLC_PAD_SEL [2:0]. These bits enable manual selection of a clock for the ...
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ADV7184 Address Register Bit Description ADC1_SW [3:0]. Manual muxing control for ADC1. 0xC4 ADC Switch 2 ADC2_SW [3:0]. Manual muxing control for ADC2. Reserved. ADC_SW_MAN_EN. This bit enables manual setting of the input signal muxing. 0xCA Field Length Count 1 ...
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Address Register Bit Description 0xE4 SD Saturation Cr SD_SAT_CR [7:0]. These bits adjust the saturation of the picture by affecting gain on the Cr channel. 0xE5 NTSC V Bit Begin NVBEG [4:0]. Number of lines after l rollover to set ...
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ADV7184 Address Register Bit Description 0xEB V Blank Control 1 PVBIELCM [1:0]. PAL VBI even field luma comb mode. PVBIOLCM [1:0]. PAL VBI odd field luma comb mode. NVBIELCM [1:0]. NTSC VBI even field luma comb mode. NVBIOLCM [1:0]. NTSC ...
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Address Register Bit Description 0xEE FB_CONTROL 2 MAN_ALPHA_VAL [6:0]. These bits determine in what proportion the video from the CVBS and RGB sources are blended. FB_CSC_MAN. 0xEF FB_CONTROL 3 FB_EDGE_SHAPE [2:0]. CNTR_ENABLE. FB_SP_ADJUST. 0xF0 FB_CONTROL 4 FB_DELAY [3:0]. Reserved. 0xF1 ...
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ADV7184 Address Register Bit Description ADC3_SW [3:0]. 0xF4 Drive Strength DR_STR_S [1:0]. These bits select the drive strength for the sync output signals. DR_STR_C [1:0]. These bits select the drive strength for the clock output signal. DR_STR [1:0]. These bits ...
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USER SUB MAP The collective name for the subaddress registers in Table 106 is user sub map. To access the user sub map, SUB_USR_EN in Register Address 0x0E (user map) must be programmed to 1. Table 106. User Sub Map ...
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ADV7184 Address Dec Hex Register Name 116 74 VDP_LINE_01E RW VBI_DATA_ VBI_DATA_P21_ P21_N19.3 N19.2 117 75 VDP_LINE_01F RW VBI_DATA_ VBI_DATA_P22_ P22_N20.3 N20.2 118 76 VDP_LINE_020 RW VBI_DATA_ VBI_DATA_P23_ P23_N21.3 N21.2 119 77 VDP_LINE_021 RW VBI_DATA_ VBI_DATA_P24_ P24_N22.3 ...
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Table 107 provides a detailed description of the registers located in the user sub map. Table 107. User Sub Map Detailed Description Address Register Bit Description 0x40 Interrupt Configuration 0 INTRQ_OP_SEL [1:0]. Interrupt drive level select. MPU_STIM_INTRQ. Manual interrupt set ...
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ADV7184 Address Register Bit Description 0x45 Raw Status 2 (Read Only) CCAPD. Reserved. EVEN_FIELD. Reserved. MPU_STIM_INTRQ. 0x46 Interrupt Status 2 CCAPD_Q. (Read Only) GEMD_Q. Reserved. SD_FIELD_CHNGD_Q. Reserved. Reserved. MPU_STIM_INTRQ_Q. 0x47 Interrupt Clear 2 CCAPD_CLR. (Write Only) GEMD_CLR. Reserved. SD_FIELD_CHNGD_CLR. Reserved. ...
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Address Register Bit Description 0x4A Interrupt Status 3 SD_OP_CHNG_Q. This bit indicates if the (Read Only frame rate is at output. SD_V_LOCK_CHNG_Q. SD_H_LOCK_CHNG_Q. SD_AD_CHNG_Q. SD autodetect changed. SCM_LOCK_CHNG_Q. SECAM lock. PAL_SW_LK_CHNG_Q. Reserved. Reserved. ...
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ADV7184 Address Register Bit Description VDP_GS_VPS_PDC_UTC_CHNG_Q. See Register 0x9C, Bit 5, of the user sub map to determine whether an interrupt is issued for a change in detected data or when data is detected regardless of content. Reserved. VDP_VITC_Q. Reserved. ...
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Address Register Bit Description 0x62 VDP_ADF_Config_1 ADF_DID [4:0]. ADF_MODE [1:0]. ADF_ENABLE. 0x63 VDP_ADF_Config_2 ADF_SDID [5:0]. Reserved. DUPLICATE_ADF. 0x64 VDP_LINE_00E VBI_DATA_P318 [3:0]. Reserved. MAN_LINE_PGM. 0x65 VDP_LINE_00F VBI_DATA_P319_N286 [3:0]. VBI_DATA_P6_N23 [3:0]. 0x66 VDP_LINE_010 VBI_DATA_P320_N287 [3:0]. VBI_DATA_P7_N24 [3:0]. 0x67 VDP_LINE_011 VBI_DATA_P321_N288 [3:0]. VBI_DATA_P8_N25 ...
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ADV7184 Address Register Bit Description 0x6F VDP_LINE_019 VBI_DATA_P329_N277 [3:0]. VBI_DATA_P16_N14 [3:0]. 0x70 VDP_LINE_01A VBI_DATA_P330_N278 [3:0]. VBI_DATA_P17_N15 [3:0]. 0x71 VDP_LINE_01B VBI_DATA_P331_N279 [3:0]. VBI_DATA_P18_N16 [3:0]. 0x72 VDP_LINE_01C VBI_DATA_P332_N280 [3:0]. VBI_DATA_P19_N17 [3:0]. 0x73 VDP_LINE_01D VBI_DATA_P333_N281 [3:0]. VBI_DATA_P20_N18 [3:0]. 0x74 VDP_LINE_01E VBI_DATA_P334_N282 [3:0]. VBI_DATA_P21_N19 ...
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Address Register Bit Description GS_PDC_VPS_UTC_CLEAR. Reserved. VITC_CLEAR. Reserved. 0x79 VDP_CCAP_DATA_0 CCAP_BYTE_1 [7:0]. (Read Only) 0x7A VDP_CCAP_DATA_1 CCAP_BYTE_2 [7:0]. (Read Only) 0x7D VDP_CGMS_WSS_DATA_0 CGMS_CRC [5:2]. (Read Only) Reserved. 0x7E VDP_CGMS_WSS_DATA_1 CGMS_WSS [13:8]. (Read Only) CGMS_CRC [1:0]. 0x7F VDP_CGMS_WSS_DATA_2 CGMS_WSS [7:0]. (Read ...
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ADV7184 Address Register Bit Description 0x9C VDP_OUTPUT_SEL Reserved. WSS_CGMS_CB_CHANGE. GS_VPS_PDC_UTC_CB_CHANGE. I2C_GS_VPS_PDC_UTC [1:0]. 1 Shading indicates default settings. Bit Comments Disable content-based updating of CGMS and WSS ...
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PCB LAYOUT RECOMMENDATIONS The ADV7184 is a high precision, high speed mixed-signal device. To achieve the maximum performance from the part important to have a well laid out PCB board. The following is a guide for designing a ...
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ADV7184 DIGITAL INPUTS The digital inputs on the ADV7184 are designed to work with 3.3 V signals and are not tolerant signals. Extra compo- nents are needed logic signals are required to be applied ...
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TYPICAL CIRCUIT CONNECTION An example of how to connect the ADV7184 video decoder is shown in Figure 52. For a detailed schematic diagram for the ADV7184, refer to the ADV7184 evaluation note, which can be obtained from an Analog Devices ...
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... ORDERING GUIDE 1 Model Temperature Range 2 ADV7184BSTZ −40°C to +85°C EVAL-ADV7184EB 1 The ADV7184 is a Pb-free, environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to withstand surface-mount soldering 255°C (±5°C). In addition backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220° ...