AD1895AYRSRL Analog Devices Inc, AD1895AYRSRL Datasheet

IC SAMP-RATEHP/CONV 24BIT 28SSOP

AD1895AYRSRL

Manufacturer Part Number
AD1895AYRSRL
Description
IC SAMP-RATEHP/CONV 24BIT 28SSOP
Manufacturer
Analog Devices Inc
Type
Sample Rate Converterr
Datasheet

Specifications of AD1895AYRSRL

Rohs Status
RoHS non-compliant
Applications
Automotive Audio, receivers, set-top boxes
Voltage - Supply, Digital
3.13 V ~ 3.46 V
Mounting Type
Surface Mount
Package / Case
28-SSOP
For Use With
EVAL-AD1895EB - BOARD EVAL FOR AD1895
Voltage - Supply, Analog
-
Lead Free Status / RoHS Status
Not Compliant

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a
REV. B
PRODUCT OVERVIEW
The AD1895 is a 24-bit, high performance, single-chip, second
generation asynchronous sample rate converter. Based upon
Analog Devices’ experience with its first asynchronous sample
rate converter, the AD1890, the AD1895 offers improved perfor-
mance and additional features. This improved performance
includes a THD + N range of –115 dB to –122 dB depending
on sample rate and input frequency, 128 dB (A-Weighted)
dynamic range, 192 kHz sampling frequencies for both input and
output sample rates, improved jitter rejection, and 1:8 upsampling
and 7.75:1 downsampling ratios. Additional features include
more serial formats, a bypass mode, and better interfacing to
digital signal processors.
The AD1895 has a 3-wire interface for the serial input and
output ports that supports left-justified, I
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
port supports TDM Mode for daisy-chaining multiple AD1895s to
*Patents pending.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FEATURES
Automatically Senses Sample Frequencies
No Programming Required
Attenuates Sample Clock Jitter
3.3 V to 5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data
Up to 192 kHz Sample Rate
Input/Output Sample Ratios from 7.75:1 to 1:8
Bypass Mode
Multiple AD1895 TDM Daisy-Chain Mode
128 dB Signal-to-Noise and Dynamic Range
Up to –122 dB THD + N
Linear Phase FIR Filter
Hardware Controllable Soft Mute
Supports 256
Flexible 3-Wire Serial Data Port with Left-Justified,
Master/Slave Input and Output Modes
28-Lead SSOP Plastic Package
APPLICATIONS
Home Theater Systems, Automotive Audio Systems,
(A-Weighted, 20 Hz to 20 kHz BW)
Clock
I
Serial Port Modes
DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio
Effects Processors
2
S, Right-Justified (16-, 18-, 20-, 24-Bit), and TDM
f
S
, 512
f
S
, or 768
2
S, and right-justified
f
S
Master Mode
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
a digital signal processor. The serial output data is dithered down
to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is
selected. The AD1895 sample rate converts the data from the
serial input port to the sample rate of the serial output port. The
sample rate at the serial input port can be asynchronous with
respect to the output sample rate of the output serial port. The
master clock to the AD1895, MCLK, can be asynchronous to
both the serial input and output ports.
MCLK can either be generated off-chip or on-chip by the AD1895
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
board. When MCLK is synchronous to either the output or input
serial port, the AD1895 can be configured in a master mode where
MCLK is divided down and used to generate the left/right
and bit clocks for the serial port that is synchronous to MCLK.
The AD1895 supports master modes of 256 × f
768 × f
Conceptually, the AD1895 interpolates the serial input data by
a rate of 2
output sample rate. In practice, a 64-tap FIR filter with 2
polyphases, a FIFO, a digital servo loop that measures the time
difference between input and output samples within 5 ps, and a
digital circuit to track the sample rate ratio are used to perform
the interpolation and output sampling. Refer to the Theory of
Operation section. The digital servo loop and sample rate ratio
circuit automatically track the input and output sample rates.
SMODE_IN_0
SMODE_IN_1
SMODE_IN_2
MUTE_OUT
LRCLK_I
SDATA_I
192 kHz Stereo Asynchronous
MUTE_IN
BYPASS
SCLK_I
S
for both input and output serial ports.
MCLK_IN
20
and samples the interpolated data stream by the
FUNCTIONAL BLOCK DIAGRAM
MCLK_OUT
SERIAL
INPUT
CLOCK DIVIDER
Sample Rate Converter
MMODE_0
DIGITAL
MMODE_1
FIFO
PLL
MMODE_2
RESET
FILTER
FS
ROM
FS
FIR
OUT
IN
VDD_IO VDD_CORE
© Analog Devices, Inc., 2002
AD1895
OUTPUT
SERIAL
AD1895
(continued on page 15)
S
www.analog.com
, 512 × f
SMODE_OUT_0
SMODE_OUT_1
WLNGTH_OUT_0
WLNGTH_OUT_1
TDM_IN
SDATA_O
SCLK_O
LRCLK_O
S
, and
*
20

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AD1895AYRSRL Summary of contents

Page 1

FEATURES Automatically Senses Sample Frequencies No Programming Required Attenuates Sample Clock Jitter 3 Input and 3.3 V Core Supply Voltages Accepts 16-/18-/20-/24-Bit Data Up to 192 kHz Sample Rate Input/Output Sample Ratios from 7.75:1 to ...

Page 2

AD1895–SPECIFICATIONS TEST CONDITIONS, UNLESS OTHERWISE NOTED. Supply Voltages VDD_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

DIGITAL TIMING (–40 C < T < +105 C, VDD_CORE = 3 Parameter t MCLK_IN Period MCLKI f MCLK_IN Frequency MCLK t MCLK_IN Pulsewidth High MPWH t MCLK_IN Pulsewidth Low MPWL INPUT SERIAL PORT TIMING t LRCLK_I ...

Page 4

AD1895 –SPECIFICATIONS DIGITAL FILTERS (VDD_CORE = 3.3 V Parameter Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Specifications subject to change without notice. DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V Parameter Input Voltage High (V ) ...

Page 5

... Model Temperature Range AD1895AYRS –40°C to +105°C AD1895AYRSRL –40°C to +105°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1895 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...

Page 6

AD1895 Pin No. IN/OUT (I/O) Mnemonic MCLK_IN 3 OUT MCLK_OUT 4 IN SDATA_I 5 IN/OUT SCLK_I 6 IN/OUT LRCLK_I 7 IN VDD_IO 8 IN DGND 9 IN BYPASS 10 IN SMODE_IN_0 11 IN SMODE_IN_1 12 ...

Page 7

FREQUENCY – kHz TPC 1. Wideband FFT Plot (16 k Points) 0 dBFS 1 kHz Tone, 48 kHz: 48 kHz (Asynchronous) 0 –20 ...

Page 8

AD1895 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 0 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz TPC 7. Wideband FFT Plot (16 k Points) 192 kHz: 48 kHz, 0 dBFS 1 kHz Tone –50 –60 ...

Page 9

FREQUENCY – kHz TPC 13. Wideband FFT Plot (16 k Points) 96 kHz: 48 kHz, –60 dBFS ...

Page 10

AD1895 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY – kHz TPC 19. Wideband FFT Plot (16 k Points) 192 kHz: 192 kHz, 0 dBFS 80 kHz Tone 0 –20 ...

Page 11

OUTPUT SAMPLE RATE – Hz TPC 25. THD + N vs. Output Sample Rate dBFS 1 kHz Tone –119 –121 –123 –125 ...

Page 12

AD1895 –119 –121 –123 –125 –127 –129 –131 –133 –135 30000 66000 102000 48000 84000 120000 OUTPUT SAMPLE RATE – Hz TPC 31. DNR (Unweighted) vs. Output Sample Rate kHz, –60 dBFS 1 kHz Tone S_IN 0 ...

Page 13

INPUT LEVEL – dBFS TPC 37. Linearity Error, 48 kHz: 44.1 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone ...

Page 14

AD1895 –110.0 –112.5 –115.0 –117.5 –120.0 –122.5 –125.0 –127.5 –130.0 –132.5 –135.0 –137.5 –140.0 –140 –120 –100 –80 –60 INPUT LEVEL – dBFS TPC 43. THD + N vs. Input Amplitude, 48 kHz: 44.1 kHz, 1 kHz Tone –110.0 –112.5 ...

Page 15

FREQUENCY – kHz TPC 49. THD + N vs. Frequency Input, 48 kHz: 44.1 kHz, 0 dBFS –110 –120 –130 –140 –150 –160 –170 –180 2.5 5.0 ...

Page 16

AD1895 ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION Asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or different sample rate. The simplest approach to asyn- chronous sample ...

Page 17

IN INTERPOLATE LOW-PASS BY N FILTER f S_IN f FREQUENCY DOMAIN OF SAMPLES AT FREQUENCY DOMAIN OF THE INTERPOLATION SIN(X)/X OF ZERO-ORDER HOLD f FREQUENCY DOMAIN OF RESAMPLING S_OUT FREQUENCY DOMAIN AFTER RESAMPLING Figure 6. Frequency Domain of the Interpolation ...

Page 18

AD1895 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 Figure 8. Frequency Response of the Digital Servo Loop. f frequency is 30 ...

Page 19

OPERATING FEATURES RESET and Power-Down When RESET is asserted low, the AD1895 will turn off the master clock input to the AD1895, MCLK_IN, initialize all of its internal registers to their default values, and three-state all of the I/O pins. ...

Page 20

AD1895 Serial Data Ports—Data Format The Serial Data Input Port Mode is set by the logic levels on the SMODE_IN_0/SMODE_IN_1/SMODE_IN_2 pins. The serial data input port modes available are left justified, I justified (RJ), 16, 18, 20 bits, ...

Page 21

TDM MODE APPLICATION In TDM Mode, several AD1895s can be daisy-chained together and connected to the serial input port of a SHARC AD1895 contains a 64-bit parallel load shift register. When the LRCLK_O pulse arrives, each AD1895 parallel loads its ...

Page 22

AD1895 Serial Data Port Master Clock Modes Either of the AD1895 serial ports can be configured as a master serial data port. However, only one serial port can be a master, while the other has slave. In ...

Page 23

PIN 1 2.00 MAX 0.05 MIN REV. B OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 ...

Page 24

AD1895 Revision History Location 9/02—Data Sheet changed from REV REV. B. Changes to SPECIFICATIONS (Digital Performance ...

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