ADV7303AKST Analog Devices Inc, ADV7303AKST Datasheet
ADV7303AKST
Specifications of ADV7303AKST
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ADV7303AKST Summary of contents
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FEATURES High Definition Input Formats YCrCb Compliant to SMPTE293M (525 p), ITU-R.BT1358 (625 p), SMPTE274M (1080 i), SMPTE296M (720 p), and Any Other High Definition Standard Using Async Timing Mode RGB in 3 8-Bit 4:4:4 Format BTA T-1004 EDTV2 ...
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ADV7302A/ADV7303A DETAILED FEATURES High Definition Programmable Features (720 p/1080 i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control ...
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ADV7302A/ADV7303A–SPECIFICATIONS ( 2.375 V–2.625 2.375 V–3.600 DD_IO Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity, +ve 2 Differential Nonlinearity, –ve DIGITAL OUTPUTS Output Low Voltage Output ...
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ADV7302A/ADV7303A DYNAMIC SPECIFICATIONS Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR SNR SNR HDTV MODE Luma Bandwidth Chroma Bandwidth SNR SNR SNR STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma ...
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TIMING SPECIFICATIONS Parameter 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time, t ...
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ADV7302A/ADV7303A CLKIN_A P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Y7–Y0 C7–C0 CONTROL S_HSYNC, O/PS S_VSYNC CLOCK HIGH TIME, = CLOCK LOW TIME Figure 2. HD 4:2:2 Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV ...
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CLKIN_A P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Y7–Y0 C7–C0 S7– S_HSYNC, CONTROL O/PS S_VSYNC CLOCK HIGH TIME, = CLOCK LOW TIME Figure 4. HD 4:4:4 RGB Input Data Format Timing Diagram, HD RGB Input ...
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ADV7302A/ADV7303A CLKIN_A P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Y7–Y0 CONTROL S_HSYNC, O/PS S_VSYNC CLOCK HIGH TIME, = CLOCK LOW TIME Figure 6. PS 4:2:2 1 Mode at Subaddress 01h = 111) CLKIN_A t 9 S_HSYNC, CONTROL ...
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CLKIN_A @ 27MHz t 9 S_HSYNC, CONTROL S_VSYNC, I/PS S_BLANK S7–S0 Y7–Y0 CONTROL S_HSYNC, O/PS S_VSYNC Figure 8. 16-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000) CLKIN_B t 9 P_HSYNC, ...
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ADV7302A/ADV7303A CLKIN_B P_HSYNC, CONTROL P_VSYNC, I/PS P_BLANK Cb0 Y7– CLKIN_A t S_HSYNC, CONTROL S_VSYNC, I/PS S_BLANK S7–S0 Cb0 Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 8-Bit (Input Mode at Subaddress 01h ...
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P_HSYNC P_VSYNC P_BLANK Y7–Y0 S7–S0 C7– CLKCYCLES FOR 525p CLKCYCLES FOR 626p CLKCYCLES FOR 1080i CLKCYCLES FOR 720p AS RECOMMENDED BY STANDARD HSYNC FIELD PAL = 12 NTSC ...
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... In addition backward compatible with conventional tin-lead soldering processes. This means that the electroplated tin coating can be soldered with tin-lead solder pastes at conventional reflow temperatures of 220°C to 235°C. Model ADV7302AKST ADV7303AKST PIN CONFIGURATION ...
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Pin No. Mnemonic Input/Output ALSB I/O 21 SDA I/O 22 SCLK I P_HSYNC 23 I P_VSYNC P_BLANK I 31 RTC_SCR_TR I 32 CLKIN_A I RESET EXT_LF I 35, ...
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ADV7302A/ADV7303A MPU PORT DESCRIPTION The ADV7302A/ADV7303A supports a 2-wire serial (I patible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry infor- mation between any device connected to the bus. Each slave device is ...
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WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT P = STOP BIT REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7302A/ADV7303A ...
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ADV7302A/ADV7303A Subaddress Register 00h Power Mode Register NOTES When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled This control allows the internal PLL circuit to be powered ...
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Subaddress Register 02h Mode Register 0 03h RGB Matrix 0 04h RGB Matrix 1 05h RGB Matrix 2 06h RGB Matrix 3 07h RGB Matrix 4 08h RGB Matrix 5 09h RGB Matrix 6 0Ah Reserved 0Bh Reserved 0Ch Reserved ...
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ADV7302A/ADV7303A Subaddress Register 10h HD Mode Register 1 11h HD Mode Register 2 12h HD Mode Register 3 Table IV. HD Mode Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit ...
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Subaddress Register 13h HD Mode Register 4 14h HD Mode Register 5 15h HD Mode Register 6 NOTES 1 4:2:2 Input Format Only 2 4:4:4 Input Format Only REV. A Table IV. HD Mode Register (continued) Bit Description Bit 7 ...
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ADV7302A/ADV7303A Subaddress Register 16h HD Y Color 17h HD Cr Color 18h HD Cb Color 19h Reserved 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh Reserved 1Eh Reserved 1Fh Reserved 20h HD Sharpness Filter Gain 21h HD CGMS Data 0 22h ...
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Subaddress Register 38h HD Adaptive Filter Gain 1 39h HD Adaptive Filter Gain 2 3Ah HD Adaptive Filter Gain 3 3Bh HD Adaptive Filter Threshold A 3Ch HD Adaptive Filter Threshold B 3Dh HD Adaptive Filter Threshold C REV. A ...
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ADV7302A/ADV7303A Subaddress Register 3Eh Reserved 3Fh Reserved 40h SD Mode Register 0 41h Reserved 42h SD Mode Register 1 Table VII. SD Mode Registers Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...
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Subaddress Register 43h SD Mode Register 2 44h SD Mode Register 3 45h Reserved 46h Reserved 47h SD Mode Register 4 REV. A Table VII. SD Mode Registers (continued) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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ADV7302A/ADV7303A Subaddress Register 48h SD Mode Register 5 49h SD Mode Register 6 *For more detail, see Input and Output Configuration section. Table VII. SD Mode Registers (continued) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...
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Subaddress Register 4Ah SD Timing Register 0 4Bh SD Timing Register 1 4Ch SD F Register 0 SC 4Dh SD F Register 1 SC 4Eh SD F Register 2 SC 4Fh SD F Register 3 SC 50h SD F Phase ...
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ADV7302A/ADV7303A Subaddress Register 59h SD CGMS/WSS 0 5Ah SD CGMS/WSS 1 5Bh SD CGMS/WSS 2 5Ch SD LSB Register 5Dh SD Y Scale Register 5Eh SD V Scale Register 5Fh SD U Scale Register 60h SD Hue Register 61h SD ...
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Subaddress Register 64h SD DNR 1 65h SD DNR 2 66h SD Gamma A 67h SD Gamma A 68h SD Gamma A 69h SD Gamma A 6Ah SD Gamma A 6Bh SD Gamma A 6Ch SD Gamma A 6Dh SD ...
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ADV7302A/ADV7303A Subaddress Register 7Ch Reset Register *Line 23 HSYNC VSYNC Subaddress Register 7Dh Reserved 7Eh Reserved 7Fh Reserved 80h Macrovision 81h Macrovision 82h Macrovision 83h Macrovision 84h Macrovision 85h Macrovision 86h Macrovision 87h Macrovision 88h Macrovision 89h Macrovision 8Ah Macrovision ...
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INPUT AND OUTPUT CONFIGURATION STANDARD DEFINITION ONLY The 8-bit multiplexed input data is input on Pins S7–S0, with S0 being the LSB. ITU-R.BT601/ITU-R.BT656 input standards are supported. In 16-bit Input Mode, the Y pixel data is input on Pins S7–S0 ...
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ADV7302A/ADV7303A PROGRESSIVE SCAN AT 27 MHz OR 54 MHz YCrCb progressive scan data can be input at 27 MHz or 54 MHz. The input data is interleaved onto a single 8-bit bus and is input on Pins Y7–Y0. For PS ...
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Table X. Overview of All Possible Input Configurations Input Format Total Bits ITU-R.BT656 16 PS Only 8 (27 MHz Clock) 8 (54 MHz Clock HDTV Only RGB 24 ITU-R.BT656 and PS ITU-R.BT656 and PS or ...
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ADV7302A/ADV7303A OUTPUT CONFIGURATION Tables XI–XIII demonstrate what output signals are assigned to the DACs when corresponding control bits are set. RGB/YUV O/P SD DAC O/P 1 Addr 02h, Bit 5 Addr 42h, Bit ...
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TIMING MODES HD Async Timing Mode [Subaddress 10h, Bits 3–2] For any input data that does not conform to SMPTE293M, SMPTE274M, SMPTE296M, or ITU-R.BT1358 standards, an Asynchronous Timing Mode can be used to interface to the ADV7302A/ADV7303A. Timing control signals ...
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ADV7302A/ADV7303A P_HSYNC P_VSYNC 1 1 → → → NOTES For standards that do not require a tri-sync level, P_BLANK must be tied ...
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VERTICAL BLANKING INTERVAL The ADV7302A/ADV7303A accepts input data that contains VBI data [CGMS, WSS, VITS, etc and HD Modes. For SMPTE293M (525 p) standards, VBI data can be inserted on Lines each frame, or ...
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ADV7302A/ADV7303A HD 4:2:2 to 4:4:4 Interpolation Filters and Chroma SSAF It is recommended to input data in 4:2:2 Input Mode to make use of the HD chroma SSAFs on the ADV7302A/ADV7303A. This filter has pass-band response and ...
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FREQUENCY – MHz Figure 37. UV – HDTV 2 Oversampling Filter 0 –10 –20 –30 –40 –50 –60 –70 – ...
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ADV7302A/ADV7303A SD Internal Filter Response [Subaddress 42h, Bit 0] The Y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost/attenua- tion, a CIF response, and a QCIF ...
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FREQUENCY – MHz Figure 44. Luma NTSC Notch Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 45. Luma PAL ...
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ADV7302A/ADV7303A 1 0 –1 –2 –3 –4 – FREQUENCY – MHz Figure 50. Luma SSAF Filter, Programmable Attenuation 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 51. ...
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FREQUENCY – MHz Figure 56. Chroma 1.0 MHz LP Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz Figure 57. Chroma ...
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ADV7302A/ADV7303A COLOR CONTROLS AND RGB MATRIX HD Y Color Color Color [Subaddresses 16h–18h] Three 8-bit wide registers at Addresses 16h, 17h, and 18h are used to program the output color of the internal HD test pattern ...
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Example: Scale Factor = 1. Scale Value = 1. Scale Value = 665 (rounded to nearest integer Scale Value = 1010011001 Address 5Ch, SD LSB Register = 15h ...
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ADV7302A/ADV7303A Gamma Correction [Subaddresses 21h–37h for HD; Subaddresses 66h–79h for SD] Gamma correction is available for SD and HD video. For each standard there are 20 8-bit wide registers. They are used to program the gamma correction curves A and ...
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SIGNAL INPUT 0.3 200 0.5 150 1.5 100 1 100 150 LOCATION Figure 62. Signal Input (Ramp) and Selectable Gamma Output HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddresses 20h and 38h-3Dh] There ...
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ADV7302A/ADV7303A Figure 64. HD Sharpness Filter Control with Different Gain Settings for HD Sharpness Filter Gain Value HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate ...
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Table XXI. Adaptive Filter Control on Step Input Signal Address Register Setting 00h FCh 01h 38h 02h 20h 10h 00h 11h 81h 15h 80h 20h 00h 38h ACh 39h 9Ah 3Ah 88h 3Bh 28h 3Ch 3Fh 3Dh 64h All other ...
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ADV7302A/ADV7303A The Digital Noise Reduction Registers are three 8-bit wide registers. They are used to control the DNR processing. Coring Gain Border [Address 63h, Bits 3–0] These four bits are assigned to the gain factor applied to border areas. In ...
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SD ACTIVE VIDEO EDGE [Subaddress 42h, Bit 7] When the active video edge is enabled, the first three pixels and the last three pixels of the active video on the Luma Channel are scaled in such a way that maximum ...
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ADV7302A/ADV7303A 6.8 H 2.2 H DAC O/P 300R 6.8pF 18pF 300R 600R Figure 75. Example of Output for Output Filter for PS, 4 Oversampling 0 MAGNITUDE (dB) –10 GROUP DELAY (sec) –20 –30 –40 PHASE (Deg) –50 –60 10M CIRCUIT ...
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To avoid crosstalk between the DAC outputs recommended to leave as much space as possible between the tracks of the individual DAC output pins. Supply Decoupling Noise on the analog power plane can be further reduced by the ...
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ADV7302A/ADV7303A Appendix A COPY GENERATION MANAGEMENT SYSTEM HD CGMS DATA Registers 2–0 [Subaddress 12h] HD CGMS is available in 525 p Mode only, conforming to “CGMS-A EIA-J CPR1204-1, Transfer Method of Video ID information using vertical blanking interval (525 p ...
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Appendix B SD WIDE SCREEN SIGNALING [Subaddresses 59h, 5Ah, and 5Bh] The ADV7302A/ADV7303A supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7302A/ ADV7303A is ...
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ADV7302A/ADV7303A Appendix C SD CLOSED CAPTIONING [Subaddresses 51h–54h] The ADV7302A/ADV7303A supports closed captioning con- forming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd ...
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Appendix D TEST PATTERNS The ADV7302A/ADV7303A can generate SD and HD test patterns. Figure 84. NTSC Color Bars Figure 85. NTSC Black Bar (–21 mV, 0 mV, +3.5 mV, +7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV) Figure ...
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ADV7302A/ADV7303A Figure 90. 525 p Field Pattern Figure 91. 525 p Black Bar (–35 mV, 0 mV, +7 mV, +14 mV, +21 mV, +28 mV, +35 mV) Figure 92. 625 p Field Pattern Figure 93. 625 p Black Bar (–35 ...
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Table XXVII. NTSC CVBS Output on DAC A Subaddress Register Setting 00h 82h 11h 01h 40h 10h 42h 40h 44h 40h 4Ah 08h 4Ch 16h 4Dh 7Ch 4Eh F0h 4Fh 21h All other registers are set to 00h. For PAL ...
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ADV7302A/ADV7303A Appendix E SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656): Slave Option (Timing Register 0 TR0 = The ADV7302A/ADV7303A is controlled by the start active video (SAV) and end active video ...
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DISPLAY 622 623 624 625 H V EVEN FIELD F DISPLAY 309 310 311 312 H V ODD FIELD F ANALOG VIDEO REV. A VERTICAL BLANK ODD FIELD VERTICAL BLANK 318 ...
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ADV7302A/ADV7303A Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A accepts horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when ...
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Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A can generate horizon- tal SYNC and odd/even FIELD signals. A transition of the FIELD input ...
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ADV7302A/ADV7303A Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and ...
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Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A can generate horizon- tal and vertical SYNC signals. A coincident low transition of both HSYNC ...
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ADV7302A/ADV7303A Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7302A/ADV7303A accepts or generates horizontal SYNC ...
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Appendix F VIDEO OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 107. EIA 770.2 Standard Output Signals (525 p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR ...
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ADV7302A/ADV7303A Appendix G VIDEO STANDARDS SMPTE274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 ...
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ACTIVE VIDEO 522 523 524 525 ACTIVE VIDEO 622 623 624 625 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 REV. A VERTICAL BLANK Figure 113. SMPTE293M VERTICAL ...
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ADV7302A/ADV7303A 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW Revision History Location 11/02—Data Sheet changed from REV REV. A. Changes to Figure ...