PCA9500BS,118 NXP Semiconductors, PCA9500BS,118 Datasheet

IC I/O EXPANDER I2C 8B 16HVQFN

PCA9500BS,118

Manufacturer Part Number
PCA9500BS,118
Description
IC I/O EXPANDER I2C 8B 16HVQFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9500BS,118

Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
No
Frequency - Clock
400kHz
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
Includes
EEPROM, POR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3351-2
935273812118
PCA9500BS-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9500BS,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
1. General description
2. Features
The PCA9500 is an 8-bit I/O expander with an on-board 2-kbit EEPROM.
The I/O expander's eight quasi-bidirectional data pins can be independently assigned as
inputs or outputs to monitor board level status or activate indicator devices such as LEDs.
The system master writes to the I/O configuration bits in the same way as for the
PCF8574. The data for each input or output is kept in the corresponding Input or Output
register. The system master can read all registers.
The EEPROM can be used to store error codes or board manufacturing data for
read-back by application software for diagnostic purposes and is included in the I/O
expander package.
The PCA9500 has 3 address pins with internal pull-up resistors allowing up to 8 devices to
share the common two-wire I
address is the same as the PCF8574 and the fixed EEPROM I
as the PCF8582C-2, so the PCA9500 appears as two separate devices to the bus master.
The PCA9500 supports hot insertion to facilitate usage in removable cards on backplane
systems.
The PCA9501 is an alternative to the functionally similar PCA9500 for systems where a
higher number of devices are required to share the same I
required.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PCA9500
8-bit I
Rev. 04 — 15 April 2009
8 general purpose input/output expander/collector
Drop-in replacement for PCF8574 with integrated 2-kbit EEPROM
Internal 256
Self timed write cycle
4 byte page write operation
I
Internal power-on reset
Noise filter on SCL/SDA inputs
3 address pins allowing up to 8 devices on the I
No glitch on power-up
Supports hot insertion
Power-up with all channels configured as inputs
Low standby current
Operating power supply voltage range of 2.5 V to 3.6 V
2
C-bus and SMBus interface logic
2
C-bus and SMBus I/O port with 2-kbit EEPROM
8 EEPROM
2
C software protocol serial data bus. The fixed GPIO I
2
C-bus/SMBus
2
C-bus or an interrupt output is
2
C-bus address is the same
Product data sheet
2
C-bus

Related parts for PCA9500BS,118

PCA9500BS,118 Summary of contents

Page 1

PCA9500 8-bit I Rev. 04 — 15 April 2009 1. General description The PCA9500 is an 8-bit I/O expander with an on-board 2-kbit EEPROM. The I/O expander's eight quasi-bidirectional data pins can be independently assigned as inputs or outputs to ...

Page 2

... NXP Semiconductors tolerant inputs/outputs 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO16, TSSOP16, HVQFN16 3. Applications I Board version tracking and configuration ...

Page 3

... NXP Semiconductors 5. Block diagram SCL SDA Fig 1. 6. Pinning information 6.1 Pinning IO0 IO1 IO2 IO3 V Fig 2. PCA9500_4 Product data sheet 2 8-bit I PCA9500 300 k INPUT FILTER POWER-ON RESET Block diagram of PCA9500 SDA SCL PCA9500D 5 12 IO7 6 11 IO6 7 10 IO5 8 9 IO4 ...

Page 4

... NXP Semiconductors Fig 4. 6.2 Pin description Table 3. Symbol IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 SCL SDA V DD [1] HVQFN16 package supply ground is connected to both V connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region ...

Page 5

... NXP Semiconductors 7. Functional description Refer also to data from shift register Fig 5. 7.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in are incorporated on the hardware selectable address pins. The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation ...

Page 6

... NXP Semiconductors 7.3 I/O operations (Refer also to Each of the PCA9500's eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O Write mode (see is transferred from the port to the microcontroller by the Read mode (see SCL slave address (I/O expander) ...

Page 7

... NXP Semiconductors 7.3.1 Quasi-bidirectional I/Os A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current source to V heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL ...

Page 8

... NXP Semiconductors slave address (memory) SDA START condition Fig 10. Byte write 7.4.1.2 Page write A page write is initiated in the same way as the byte write. If after sending the first word of data, the STOP condition is not received, the PCA9500 considers subsequent words as data. After each data word the PCA9500 responds with an acknowledge and the two least signifi ...

Page 9

... NXP Semiconductors Fig 12. Current address read 7.4.2.2 Random read The PCA9500's random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read. The master must perform a byte write to the address location to be ...

Page 10

... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...

Page 11

... NXP Semiconductors 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL TRANSMITTER/ Fig 17. System confi ...

Page 12

... NXP Semiconductors 9. Application design-in information A central processor/controller typically located on the system main board can use the 400 kHz I status or version control type of information. The PCA9500 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data, and so on. Alternately, these devices can be used as convenient interface for board confi ...

Page 13

... NXP Semiconductors MASTER CONTROLLER SCL SDA V SS GPIO device address configured as 0100 100x for this example. EEPROM device address configured as 1010 100x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used and must be configured as outputs. ...

Page 14

... NXP Semiconductors 11. Static characteristics Table 5. Static characteristics Symbol Parameter Supply V supply voltage DD I standby current DDQ I supply current read DD1 I supply current write DD2 V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...

Page 15

... NXP Semiconductors 2 2 3 3.6 V 100 160 0 1 amb amb Fig 21. V versus Remark: Rapid fall-off in V overvoltage protection for the GPIO I/O pins. When the GPIO I/O are being used as inputs, the internal current source V resistors are required to provide sufficient V ...

Page 16

... NXP Semiconductors 12. Dynamic characteristics Table 6. Dynamic characteristics Symbol Parameter 2 [1] I C-bus timing (see Figure 22) f SCL clock frequency SCL t pulse width of spikes that must be SP suppressed by the input filter t bus free time between a STOP and START BUF condition t set-up time for a repeated START condition SU ...

Page 17

... NXP Semiconductors START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA 2 Fig 22. I C-bus timing SCL th SDA 8 bit word n Fig 23. Write cycle timing PCA9500_4 Product data sheet 2 8-bit I C-bus and SMBus I/O port with 2-kbit EEPROM bit 7 bit 6 MSB (A6) (R/W) (A7) ...

Page 18

... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 19

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 21

... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 22

... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 23

... NXP Semiconductors Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 10. Acronym ASIC CBT CDM CPU EEPROM ESD FF GPIO 2 I C-bus I/O HBM ...

Page 24

... Release date PCA9500_4 20090415 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 3 “Pin – added – changed naming convention for pins I/On to “IOn” ...

Page 25

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 26

... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.3 I/O operations . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3.1 Quasi-bidirectional I/ 7.4 Memory operations ...

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