PCA8575D,112 NXP Semiconductors, PCA8575D,112 Datasheet
PCA8575D,112
Specifications of PCA8575D,112
935283502112
PCA8575D
PCA8575D
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PCA8575D,112 Summary of contents
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PCA8575 Remote 16-bit I/O expander for I Rev. 02 — 21 March 2007 1. General description The PCA8575 provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional I The device consists of a 16-bit quasi-bidirectional ...
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... NXP Semiconductors I Gaming machines I Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Type number Topside Package mark Name PCA8575D PCA8575D SO24 PCA8575DB PCA8575DB SSOP24 PCA8575DK PCA8575 SSOP24 PCA8575PW PCA8575PW TSSOP24 PCA8575BQ 8575 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad ...
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... NXP Semiconductors data from Shift Register data to Shift Register Fig 2. Simplified schematic diagram of P00 to P17 6. Pinning information 6.1 Pinning INT AD1 AD2 P00 P01 P02 P03 P04 P05 P06 P07 V Fig 3. Pin configuration for SO24 PCA8575_2 Product data sheet ...
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... NXP Semiconductors Fig 5. Pin configuration for SSOP24 terminal 1 index area Fig 7. Pin configuration for HVQFN24 PCA8575_2 Product data sheet Remote 16-bit I/O expander for I INT AD1 2 23 SDA 22 AD2 3 SCL 21 P00 4 AD0 P01 5 20 P17 P02 6 19 P16 PCA8575DK ...
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... NXP Semiconductors 6.2 Pin description Table 2. Symbol INT AD1 AD2 P00 P01 P02 P03 P04 P05 P06 P07 V SS P10 P11 P12 P13 P14 P15 P16 P17 AD0 SCL SDA V DD [1] HVQFN and DHVQFN package die supply ground is connected to both the V pad ...
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... NXP Semiconductors 7. Functional description Refer to 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA8575 is shown in 8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 3 “ ...
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... NXP Semiconductors 8. I/O programming 8.1 Quasi-bidirectional I/O architecture The PCA8575’s 16 ports (see as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see (see Figure Every data transmission from the PCA8575 must consist of an even number of bytes, the fi ...
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... NXP Semiconductors SCL slave address SDA START condition write to port data output from port P05 output voltage P05 pull-up output current P16 output voltage P16 pull-up output current INT Fig 11. Write mode (output) 8.3 Reading from a port (Input mode) All ports programmed as input should be set to logic 1. To read, the master (microcontroller) fi ...
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SCL P0x SDA DATA 00 START condition R/W acknowledge from slave read from port 0 data into port 0 DATA 00 ...
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SCL P0x SDA DATA 00 START condition R/W acknowledge from slave read from port 0 t h(D) data into port 0 ...
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... NXP Semiconductors 8.4 Power-on reset When power is applied reset condition until V and the PCA8575 registers and I states. Thereafter V 8.5 Interrupt output (INT) The PCA8575 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see chips a kind of master function which can initiate an action elsewhere in the system. ...
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... NXP Semiconductors 9. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 17. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 10. Application design-in information 10.1 Bidirectional I/O expander applications In the 8-bit I/O expander application shown in to P07 are outputs. When used in this configuration, during a write, the input (P00 and P01) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to P07) ...
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... NXP Semiconductors 10.3 Differences between the PCA8575 and the PCF8575 The PCA8575 is a drop in replacement for the PCF8575 and can used without electrical or software modifications, but there is a difference in interrupt output release timing during the read operation. Write operations are identical. At the completion of each 8-bit write sequence the data is stored in its associated 8-bit write register at ACK or NACK. The fi ...
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... NXP Semiconductors 12. Static characteristics Table 5. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...
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... NXP Semiconductors 13. Dynamic characteristics Table 6. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and START BUF condition t hold time (repeated) START condition HD;STA t set-up time for a repeated START condition SU;STA t set-up time for STOP condition SU ...
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... NXP Semiconductors START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 21. I C-bus timing diagram PCA8575_2 Product data sheet Remote 16-bit I/O expander for I bit 7 bit 6 MSB (A6) (A7 LOW HIGH 1 /f SCL SU;DAT HD;DAT and V ...
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... NXP Semiconductors 14. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 23. Package outline SOT340-1 (SSOP24) ...
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... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) A UNIT max. 0.25 1.55 mm 1.73 0.25 0.10 1.40 0.0098 0.061 inches 0.068 0.01 0.0040 0.055 Note 1 ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Abbreviations Table 9. Acronym CDM CMOS ESD GPIO HBM I C-bus IC ID LED LSB MM MSB PLC ...
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... NXP Semiconductors 18. Revision history Table 10. Revision history Document ID Release date PCA8575_2 20070321 • Modifications: Table 5 “Static – I (Typ) for V OL – I (Typ) for V OL – I (Typ) for V OL – I (Typ) changed from <tbd> to 102 A OH – Symbol C changed Typ value from <tbd> – ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 Address map I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1 Quasi-bidirectional I/O architecture . . . . . . . . . 7 8.2 Writing to the port (Output mode ...