PCA9535D,112 NXP Semiconductors, PCA9535D,112 Datasheet
PCA9535D,112
Specifications of PCA9535D,112
935273945112
PCA9535D
Related parts for PCA9535D,112
PCA9535D,112 Summary of contents
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... The PCA9535 and PCA9535C are 24-pin CMOS devices that provide 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I developed to enhance the NXP Semiconductors family of I improvements include higher drive capability I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc ...
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... NXP Semiconductors I No glitch on power-up I Internal power-on reset I 16 I/O pins which default to 16 inputs 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA ...
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... NXP Semiconductors 4. Block diagram SCL SDA Fig 1. PCA9535_PCA9535C_5 Product data sheet 2 16-bit I C-bus and SMBus, low power I/O port with interrupt PCA9535 PCA9535C 2 I C-BUS/SMBus CONTROL INPUT FILTER POWER-ON RESET Remark: All I/Os are set to inputs at reset. Block diagram of PCA9535; PCA9535C Rev. 05 — ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 V Fig 2. terminal 1 index area IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 Fig 4. PCA9535_PCA9535C_5 Product data sheet 2 16-bit I C-bus and SMBus, low power I/O port with interrupt 1 24 INT ...
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... NXP Semiconductors 5.2 Pin description Table 3. Symbol INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 V SS IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 A0 SCL SDA V DD [1] HVQFN24 and HWQFN24 package die supply ground is connected to both the V center pad. The V ...
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... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Fig 6. 6.2 Registers 6.2.1 Command byte The command byte is the first byte to follow the address byte during a write transmission used as a pointer to determine which of the following registers will be written or read. Table 4. Command PCA9535_PCA9535C_5 ...
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... NXP Semiconductors 6.2.2 Registers 0 and 1: Input port registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. ...
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... NXP Semiconductors 6.2.5 Registers 6 and 7: Configuration registers This register configures the directions of the I/O pins bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output ...
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... NXP Semiconductors data from shift register data from shift register configuration write pulse read pulse data from shift register write polarity (1) PCA9535C I/Os are open-drain only. The portion of the PCA9535 schematic marked inside the Fig 7. 6.5 Bus transactions 6.5.1 Writing to the port registers Data is transmitted to the PCA9535/PCA9535C by sending the device address and setting the least signifi ...
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SCL slave address SDA START condition R/W write to port data out from port 0 data out from port 1 Fig 8. Write ...
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... NXP Semiconductors 6.5.2 Reading the port registers In order to read data from the PCA9535/PCA9535C, the bus master must first send the PCA9535/PCA9535C address with the least significant bit set to a logic 0 (see “PCA9535; PCA9535C device determines which register will be accessed. After a restart, the device address is sent again, but this time the least signifi ...
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INT INT t t v(INT_N) rst(INT_N) SCL R/W slave address I0.x SDA ...
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DATA 00 t h(D) data into port 1 DATA 10 INT t t v(INT_N) rst(INT_N) SCL R/W slave address I0.x SDA ...
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... NXP Semiconductors 6.5.3 Interrupt output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read (see output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around ...
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... NXP Semiconductors 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL ...
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... NXP Semiconductors 8. Application design-in information MASTER CONTROLLER SCL SDA INT GND Device address configured as 1110 100Xb for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs. Fig 17. Typical application ...
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... NXP Semiconductors 8.1 Minimizing I When the PCA9535 I/Os are used to control LEDs, they are normally connected to V through a resistor as shown in off the I/O V becomes lower than V Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V Figure 18 than the LED supply voltage by at least 1 ...
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... NXP Semiconductors 10. Static characteristics Table 14. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...
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... NXP Semiconductors [2] Each I/O must be externally limited to a maximum and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. [3] The total current sourced by all I/Os must be limited to 160 mA. PCA9535C does not source current and does not have the V specifi ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 20. Definition of timing on the I START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 21. I C-bus timing diagram SCL IOn Fig 22. t PCA9535_PCA9535C_5 Product data sheet 2 16-bit I ...
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... NXP Semiconductors 12. Test information Fig 23. Test circuitry for switching times Fig 24. Load circuit PCA9535_PCA9535C_5 Product data sheet 2 16-bit I C-bus and SMBus, low power I/O port with interrupt V I PULSE GENERATOR R = load resistor load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance of Z ...
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... NXP Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 18. Acronym ACPI CBT CDM CMOS DUT ESD FET GPIO HBM I C-bus IC LED ...
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... NXP Semiconductors 17. Revision history Table 19. Revision history Document ID Release date PCA9535_PCA9535C_5 20080915 • Modifications: Table 3 “Pin PCA9535_PCA9535C_4 20080731 PCA9535_PCA9535C_3 20071004 PCA9535_2 20040930 (9397 750 12896) PCA9535_1 20030627 (9397 750 11681) PCA9535_PCA9535C_5 Product data sheet PCA9535; PCA9535C 2 16-bit I C-bus and SMBus, low power I/O port with interrupt ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Registers 6.2.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.2 Registers 0 and 1: Input port registers . . . . . . . 7 6 ...