SI3056-D-FS Silicon Laboratories Inc, SI3056-D-FS Datasheet
SI3056-D-FS
Specifications of SI3056-D-FS
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SI3056-D-FS Summary of contents
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... Fax machines Multi-function printers Description The Si3056 is an integrated direct access arrangement (DAA) with a programmable line interface to meet global telephone line requirements. Available in two 16-pin small outline packages, it eliminates the need for an analog front end (AFE), isolation transformer, relays, opto-isolators, and 4-wire hybrid. The Si3056 dramatically reduces the number of discrete components and cost required to achieve compliance with global regulatory requirements ...
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Si3018/19/10 2 Rev. 1.05 ...
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... Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. AOUT PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1. Upgrading from the Si3034/35/44 to Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2. Line-Side Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.5. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6. Transmit/Receive Full Scale Level (Si3019 Line-Side Only ...
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... Si3018/19/10 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10. Evaluation Board Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Silicon Laboratories Si3056 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 4 Rev. 1.05 ...
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... The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the Si3056 and any Si3018 or Si3019 are used. See Figure 17 on page 18 for typical application schematic. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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Si3018/19/10 Table 2. Loop Characteristics = = see (V 3 ° Parameter Symbol DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC Termination ...
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Table 3. DC Characteristics 3 ° Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 1 ...
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Si3018/19/10 Table 4. AC Characteristics (V = 3 °C; see Figure 17 on page 18 Parameter 1 Sample Rate 1 PLL Output Clock Frequency Transmit Frequency Response Receive Frequency Response ...
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Table 4. AC Characteristics (Continued 3 °C; see Figure 17 on page 18 Parameter Receive Total Harmonic 8,9 Distortion Receive Total Harmonic 8,9 Distortion Dynamic Range (caller ID ...
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... Si3018/19/10 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3056 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict functional operation to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods might affect device reliability. Table 6. Switching Characteristics— ...
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Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 3 ° pF Parameter Cycle time, SCLK SCLK Duty Cycle Delay Time, SCLK↑ to ...
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Si3018/19/10 Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK ↑ to ...
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Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 3 ° pF Parameter Cycle Time, SCLK SCLK Duty ...
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Si3018/19/10 Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = Charge Pump 3 Parameter Cycle Time, MCLK Setup Time, FSYNC ↑ before MCLK ↓ * Delay ...
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Table 11. Digital FIR Filter Characteristics—Transmit and Receive (V = 3.0 to 3.6 V, Sample Rate = 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Note: Typical FIR filter ...
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Si3018/19/10 Figure 7. FIR Receive Filter Response Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. 16 Figure 9. FIR Transmit Filter Response Figure 10. FIR ...
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Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response Si3018/19/10 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay Rev. ...
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Si3018/19/10 2. Typical Application Schematic 18 Rev. 1.05 ...
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... W, 5% 3.65 kohm, 1 2.49 kohm, 1 100 kohm, 1/ Mohm, 1/ Mohm, 1/ 536 ohm, 1 73.2 ohm, 1 56.2 ohm, 1/ ohm, 1/16 W 4.7 kohm,, 1/ Si3056 Si3018/19/10 Rev. 1.05 Si3018/19/10 Supplier(s) Panasonic, Murata, Vishay Venkel, SMEC Panasonic Venkel, SMEC Venkel, SMEC Panasonic, Murata, Vishay Venkel, SMEC ...
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... Si3018/19/10 4. AOUT PWM Output Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3056 for call progress monitoring purposes. Set the PWME bit (Register 1, bit 3) to enable this mode AOUT Figure 18. AOUT PWM Circuit for Call Progress Table 13. Component Values— ...
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... The Si3056 DAA is software programmable to meet global requirements and is compliant with FCC, TBR21, JATE, and other country-specific PTT specifications as shown in Table 16 on page 26. In addition, the Si3056 meets the most stringent worldwide requirements for out-of-band energy, emissions, immunity, high-voltage surges, and safety, including FCC Part 15 and 68, EN55022, EN55024, and many other standards ...
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... Yes (SW polling) Line I/V Threshold Detection Ring Qualification Wake-on-Ring Support HW Interrupts Ring detect only Integrated Fixed Analog Hybrid Programmable Digital Hybrid Full Scale Transmit/Receive Level 22 Table 14. New Si3056 Features Si3044 Si3021 Si3015 Si3010 Yes Yes SSI SSI 3 3 kbps 2400 bps ...
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Table 15. Country Specific Register Settings Register 16 31 Country OHS OHS2 Argentina Australia 1 0 Austria 0 1 Bahrain 0 1 Belgium 0 1 Brazil 0 0 Bulgaria 0 1 Canada 0 0 Chile 0 0 ...
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Si3018/19/10 Table 15. Country Specific Register Settings (Continued) Register 16 31 Country OHS OHS2 Lebanon 0 1 Luxembourg 0 1 Macao Malaysia 0 0 Malta 0 1 Mexico 0 0 Morocco 0 1 Netherlands 0 1 New ...
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... Line-Side Only) The Si3056 supports programmable maximum transmit and receive levels. The default signal level supported by the Si3056 is 0 dBm into a 600 Ω load. Two additional modes of operation offer increased transmit and receive ® level capability to enable use of the DAA in applications that require higher signal levels ...
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... Detection" on page 35.) 5.8.1. Line Voltage Measurement The Si3056 device reports line voltage with the LVS[7:0] bits (Register 29) in both on- and off-hook states with a resolution per bit. The accuracy of these bits is approximately ±10%. Bits 0 through 6 of this register indicate the value of the line voltage in 2s compliment format ...
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Several events occur in the DAA when the OFHK pin is asserted or the OH bit is set. There is a 250 µ s latency to allow the off-hook command to be communicated to the line-side device. Once the line-side ...
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... FCC mode 500 ms after the initial off-hook. This satisfies the Australian dc termination requirements. 5.12. AC Termination The Si3056 has four ac termination impedances with the Si3018 line-side device and sixteen ac termination impedances with the Si3019 line-side device. The ACT and ACT2 bits select the ac impedance on the Si3018 line-side device ...
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... This hybrid circuit is adjusted for each ac termination setting selected. The Si3056 also offers a digital filter stage for additional near-end echo cancellation. For each ac termination setting selected, the eight programmable hybrid registers (Registers 45-52) can be programmed with coefficients to provide increased cancellation of real- world line anomalies ...
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... Ringer Impedance and Threshold The ring detector in many DAAs is ac coupled to the line with a large 1 µF, 250 V decoupling capacitor. The ring detector on the Si3056 is resistively coupled to the line. This produces a high ringer impedance to the line of approximately 20 M Ω to meet the majority of country PTT specifications, including FCC and TBR21 ...
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... Billing tone detection is enabled with the BTE bit (Register 17, bit 2). Billing tones less than 1.1 V the line are filtered out by the low pass digital filter on the Si3056. The ROV bit is set when a line signal is greater than 1 indicating a receive overload PK condition ...
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... Caller ID The Si3056 can pass caller ID data from the phone line to a caller ID decoder connected to the serial port. 5.21.1. Type I Caller ID Type I Caller ID sends the CID data while the phone is on-hook. ...
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The host processor must detect the presence of this tone. 2. The DAA must then check for another parallel device on the same line. This is accomplished by briefly going on-hook, measuring the line voltage, and then returning ...
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... CO at this time. 6. This example uses the OH bit to put the Si3056 into an off-hook state. The OFHK pin can also be used to accomplish this. To use the OFHK pin instead of the OH bit, simply enable the OHE bit (Register 5, bit 1) and drive the OFHK pin low during the preceding sequence ...
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... Overload Detection The Si3056 can be programmed to detect an overload condition that exceeds the normal operating power range of the DAA circuit. To use the overload detection feature, the following steps should be followed: 1. Set the OH bit (Register 5, bit off-hook, and wait allow line transients to settle. ...
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... In serial mode 2 (refer to the “5.26.Digital Interface” section), the Si3056 operates as a slave device. The clock generator is configured based on the SRC register to generate the required internal clock frequencies. In this mode, PLL2 is powered-down. For further details of slave mode operation, see " ...
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... M1 Decoder Figure 26. Update Rate of PLL1 In serial mode the Si3056 operates as a master, where the master clock (MCLK input, the serial data clock (SCLK output, and the frame sync signal (FSYNC output. The MCLK frequency and the value of the sample rate control registers 7, 8, and 9 determine the sample rate (Fs) ...
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... The Si3056 supports the operation eight Si3056 devices on a single serial bus. The master Si3056 must be configured in serial mode 1. Configure the slave(s) Si3056 in serial mode 2. Figure 36 on page 47 shows a typical master/slave connection using three Si3056 devices. When in serial mode 2, FSYNC becomes an input, RGDT/FSD/M1 becomes the delay frame sync output, and FC/RGDT becomes the ring detection output ...
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... PDL bit must be clear before enabling sleep mode. The PDN bit must then be set. When the Si3056 is in sleep mode the MCLK signal must remain active. In low-power sleep mode with MCLK active, the Si3056 is non- functional except for the isolation link and the RGDT signal ...
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... Note: All test modes are mutually exclusive. If more than one test mode is enabled concurrently, the results are unpredictable. 5.31. Exception Handling The Si3056 provides several mechanisms to determine if an error occurs during operation. Through the secondary frames of the serial link, the controlling systems can read several status bits. ...
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... With the Si3056 the system designer can determine the revision of the Si3056 and/or the line-side device. The REVA[3:0] bits (Register 11, bits 3:0) identify the revision of the Si3056. The REVB[3:0] bits (Register 13, bits 3:0) identify the revision of the line-side device. Table 22 lists revision values for all devices and might contain future revisions not yet in existence ...
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Si3018/19/10 Com m unications Fram e 1 (CF1) FSYNC Prim ary FC 0 D15–D0 SDI XMT Data SDO RCV Data 16 SCLKS 128 SCLKS Figure 28. Hardware FC/RGDT Secondary Request FSYNC (mode 0) FSYNC (mode 1) SDI SDO Figure 29. ...
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FSYNC (mode 0) FSYNC (mode 1) SDI R/W SDO Figure 30. Secondary Communication Data Format—Write Cycle Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg ...
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Si3018/19/10 Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 ...
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Si3018/19/10 Rev. 1.05 45 ...
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... SDI FSYNC INT0 Figure 35. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem) 46 128 SCLKs 1 M aster Slave1 M aster 0 M aster Slave1 M aster MCLK Si3056 MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD/M1 47 kΩ 47 kΩ 47 kΩ kΩ Si3000 SCLK MCLK ...
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... Figure 36. Typical Connection for Multiple DAAS Rev. 1.05 Si3018/19/10 MCLK Si3056—Master MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD/M1 VCC M0 47 kΩ Si3056—Slave 1 MCLK NC SCLK FSYNC SDI SDO RGDT/FSD/M1 M0 Si3056—Slave 2 MCLK NC SCLK FSYNC SDI SDO VCC 47 kΩ RGDT/FSD/ ...
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Si3018/19/10 6. Control Registers Register Name 1 Control 1 2 Control 2 3 Interrupt Mask 4 Interrupt Source 5 DAA Control 1 6 DAA Control 2 7 Sample Rate Control 8 PLL Divide N 9 PLL Divide M 10 DAA ...
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Register 1. Control 1 Bit Name SR PWMM[1:0] Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their reset value. ...
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Si3018/19/10 Register 2. Control 2 Bit Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring ...
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Register 3. Interrupt Mask Bit Name RDTM ROVM FDTM Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTM Ring Detect Mask ring signal does not cause an interrupt on the AOUT/INT ...
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Si3018/19/10 Register 4. Interrupt Source Bit Name RDTI ROVI FDTI Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring ...
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Bit Name 1 DLCSI Delta Loop Current Sense Interrupt 0 = The LCS bits have not changed value The LCS bits have changed value; a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to ...
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Si3018/19/10 Register 6. DAA Control 2 Bit Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this bit. ...
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Register 8. PLL Divide N Bit Name Type Reset settings = 0000_0000 (serial mode 0, 1) Reset settings = 0001_0011 (serial mode 2) Bit Name 7:0 N[7:0] PLL N Divider. Contains the (value –1) for determining the ...
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Si3018/19/10 Register 11. System-Side and Line-Side Device Revision Bit Name LSID[3:0] Type R Reset settings = xxxx_xxxx Bit Name 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values depending on ...
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Register 13. Line-Side Device Revision Bit Name 0 Type Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero This bit always reads a zero. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the ...
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... Daisy-Chain Enable Daisy-chaining disabled Enables the Si3056 to operate with slave devices on the same serial bus. The FC/RGDT signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the delayed frame sync signal. ALL other bits in this register are ignored if DCE = 0. ...
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Register 15. TX/RX Gain Control 1 Bit Name TXM ATX[2:0] Type R/W R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 ...
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Si3018/19/10 Register 16. International Control 1 Bit Name ACT2 OHS ACT Type RW R/W R/W Reset settings = 0000_0000 Bit Name 7 ACT2 AC Termination Select 2 (Si3018 line-side device only). Works with the ACT bit to ...
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Register 17. International Control 2 Bit Name CALZ MCAL CALD Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the existing calibration data. This ...
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Si3018/19/10 Register 18. International Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero or one. 1 RFWE Ring Detector Full-Wave Rectifier Enable. When RNGV (Register 24) is disabled, this bit ...
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Register 19. International Control 4 Bit Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV in Register 17, but clears ...
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Si3018/19/10 Register 20. Call Progress Receive Attenuation Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal ...
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Register 22. Ring Validation Control 1 Bit Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name 7:6 RDLY[1:0] Ring Delay Bits 1 and 0. These bits, in combination with the RDLY[2] bit (Register 23), set the ...
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Si3018/19/10 Register 23. Ring Validation Control 2 Bit Name RDLY[2] RTO[3:0] Type R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), set the ...
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Register 24. Ring Validation Control 3 Bit Name RNGV Type R/W R Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled ...
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Si3018/19/10 Register 25. Resistor Calibration Bit Name RCALS RCALM RCALD Type R R/W R/W Reset settings = xx0x_xxxx Bit Name 7 RCALS Resistor Auto Calibration Resistor calibration is not in progress Resistor calibration ...
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Register 26. DC Termination Control Bit Name DCV[1:0] MINI[1:0] Type R/W Reset settings = 0000_0000 Bit Name 7:6 DCV[1:0] TIP/RING Voltage Adjust. Adjust the voltage on the DCT pin of the line-side device, which affects the TIP/RING ...
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Si3018/19/10 Register 27. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not read or write. Register 28. Loop Current Status Bit Name Type Reset settings = 0000_0000 Bit Name ...
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Register 30. AC Termination Control (Si3019 line-side device only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 FULL2 Enhanced Full Scale (2X) Transmit and Receive Mode (Si3019 line-side Revision E ...
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Si3018/19/10 Register 31. DAA Control 3 Bit Name FULL FOH[1:0] Type R/W R/W Reset settings = 0010_0000 Bit Name 7 FULL Full Scale Transmit and Receive Mode (Si3019 line-side device only Default Transmit/receive ...
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Register 32-37. Reserved Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 38. TX Gain Control 2 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 ...
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Si3018/19/10 Register 39. RX Gain Control 2 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] ...
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Register 40. TX Gain Control 3 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TXG3[3:0] bits ...
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Si3018/19/10 Register 41. RX Gain Control 3 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] ...
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Register 43. Line Current/Voltage Threshold Interrupt (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 CVT[7:0] Current/Voltage Threshold. Determines the threshold at which an interrupt is generated from either the LCS or ...
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Si3018/19/10 Register 45. Programmable Hybrid Register 1 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits are programmed with a coefficient value to adjust the hybrid response to reduce ...
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Register 47. Programmable Hybrid Register 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3018/19/10 Register 49. Programmable Hybrid Register 5 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits are programmed with a coefficient value to adjust the hybrid response to reduce ...
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Register 51. Programmable Hybrid Register 7 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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... Guarded Clear Enable (Line-side Revision E or later). 1 GCE This bit (in conjunction with the RZ bit set to 1), enables the Si3056 to meet BT’s Guarded Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw approximately 2 current from the line while on-hook. ...
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... A —UL1950 3 PPENDIX RD Although designs using the Si3056 comply with the UL1950 3rd edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 37 shows two designs that can pass the UL1950 overvoltage tests and electromagnetic emissions. The ...
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... Si3056. 7 FC/RGDT Secondary Transfer Request Input/Ring Detect. An optional signal to instruct the Si3056 that control data is being requested in a sec- ondary frame. When daisy chain is enabled, this pin becomes the ring detect output. Produces an active low rectified version of the ring signal. 8 RESET Reset Input ...
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... GND Ground. Connects to the system digital ground Analog Supply Voltage. A Provides the analog supply voltage for the Si3056 Mode Select 0. The first of two mode select pins that selects the operation of the serial port/DSP inter- face. 15 RGDT/FSD/M1 Ring Detect/Delayed Frame Sync/Mode Select 1. ...
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Si3018/19/10 8. Pin Descriptions: Si3018/19/10 Table 25. Si3018/19/10 Pin Descriptions Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves ...
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Table 25. Si3018/19/10 Pin Descriptions (Continued) Pin # Pin Name 13 QB Transistor Base. Connects to the base of transistor Q4. 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground ...
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... Si3018/19/10 1,2 9. Ordering Guide Part Number Si3056-KS Si3056-X-FS Part Number Si3010-X-FS Si3018-X-FS Si3019-X-FS Notes: 1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel. 88 System Side Package Lead Free SOIC-16 No SOIC-16 Yes ...
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... Parallel Port Si3056PPT1-EVB Si3019 Parallel Port Si3056PPT2-EVB Si3010 Parallel Port Si3056SSI-EVB Si3018 Serial Interface with Buffer Direct Connection to processor Si3056SSI1-EVB Si3019 Serial Interface with Buffer Si3056SSI2-EVB Si3010 Serial Interface with Buffer Si3056DC-EVB Si3018 Daughtercard Only Si3056DC1-EVB Si3019 Daughtercard Only Si3056DC2-EVB Si3010 ...
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... Si3018/19/10 11. Package Outline: 16-Pin SOIC Figure 38 illustrates the package details for the Si3056/18/19/10. Table 26 lists the values for the dimensions shown in the illustration aaa - Seating Plane Figure 38. 16-pin Small Outline Integrated Circuit (SOIC) Package Table 26. Package Diagram Dimensions 90 bbb -B- θ A -C- A1 γ ...
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... Updated Tables 2, 3, & 4 based on production test results. Updated Table 4 with footnotes to explain expected DR and THD when using the Si3056 with the Si3010 low-speed line-side device. Updated BOM. Updated Country Specific Register Settings. Updated the following functional descriptions: ...
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... Updated Table 18 on page 28 (changed act for ACIM = 1010). Added Figure 6 on page 14. Updated "5.25.Clock Generation" on page 36. Updated Table 23, “Register Summary,” on page 48. Updated Table 24, “Si3056 Pin Descriptions,” on page 84. Updated Figure 19 on page 26. Updated "5.6.Transmit/Receive Full Scale Level (Si3019 Line-Side Only)" on page 25 of Functional description to include new enhanced full scale mode ...
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... Application Note 67: Layout Guidelines Application Note 72: Ring Detection/Validation with the Si305x DAAs Application Note 84: Digital Hybrid with the Si305x DAAs Si30xxPPT-EVB Data Sheet Si30xxSSI-EVB Data Sheet Note: Refer to www.silabs.com for a current list of support documents for this chipset. Si3056 S D UPPORT OCUMENTATION Rev. 1.05 Si3018/19/10 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders. ...