SI3015-BS Silicon Laboratories Inc, SI3015-BS Datasheet
SI3015-BS
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SI3015-BS Summary of contents
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’ Features Complete DAA includes: AC’97 2.1 Compliant Primary or Secondary Codec Global Phone Line Interface Compliant with FCC, CTR21, JATE, and Other PTTs 84 dB Dynamic Range TX/RX ...
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Si3038 2 Rev. 2.01 ...
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Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . ...
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Si3038 Electrical Specifications Table 1. Recommended Operating Conditions 1 Parameter 3 Ambient Temperature Si3024 Supply Voltage, Analog 4 Si3024 Supply Voltage, Digital 4 Si3024 Supply Voltage, Digital Notes: 1. The Si3038 specifications are guaranteed when the typical application circuit (including ...
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Table 2. Loop Characteristics (V = 3 Charge Pump Parameter DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC ...
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Si3038 Table 3. DC Characteristics 4. 4. Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage ...
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Table 5. AC Characteristics (V = 3 Charge Pump Parameter Transmit Frequency Response Receive Frequency Response 1 Transmit Full Scale Level 1,2 Receive Full Scale Level 3 Dynamic Range 3 Dynamic Range ...
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Si3038 Table 6. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3024 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional ...
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Table 9. AC Link Timing Characteristics—Clocks (V = 3 Charge Pump Parameter BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter BIT_CLK High Pulse Width* BIT_CLK low Pulse Width* SYNC Frequency SYNC Period SYNC ...
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Si3038 Table 10. AC Link Timing Characteristics—Data Setup and Hold (V = 3 Charge Pump Parameter Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK SYNC SDATA_OUT SDATA_IN ...
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Table 12. AC Link Timing Characteristics— Low Power Mode Timing (V = 3 Charge Pump Parameter End of Slot 2 to BIT_CLK, SDATA_IN Low Figure 7. AC-Link Low Power Mode Timing Diagram ...
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Si3038 Table 14. Digital FIR Filter Characteristics—Transmit and Receive (V = 3 Charge Pump, Sample Rate = 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation ...
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Input Frequency—Hz Figure 9. FIR Receive Filter Response Input Frequency—Hz Figure 10. FIR Receive Filter Passband Ripple For Figures 9–12, all filter plots apply to a sample rate kHz. The filters scale with the sample rate ...
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Si3038 Input Frequency—Hz Figure 13. IIR Receive Filter Response Input Frequency—Hz Figure 14. IIR Receive Filter Passband Ripple For Figures 13–16, all filter plots apply to a sample rate kHz. The filters scale with the sample ...
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Input Frequency—Hz Figure 17. IIR Receive Group Delay Input Frequency—Hz Figure 18. IIR Transmit Group Delay Rev. 2.01 Si3038 15 ...
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No Ground Plane In DAA Section 24.576 MHz C10 C3 Z4 C34 C35 Y1 D3 BAV99 R8 R7 R15 ID1 MCLK/XIN GPIO_A 2 15 XOUT GPIO_B 3 14 BITCLK BIT_CLK ID1 ...
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Bill of Materials Table 16. Global Component Values—Si3038 Chipset 1 Component C1,C4 C2,C11,C23,C28,C29,C31,C32 0.22 µ X7R,±20 0.1 µ Elec/Tant, ±20% C6,C10,C16 C7,C8 560 pF, 250 V, X7R, ±20 nF, 250 V, X7R, ...
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Si3038 Table 17. FCC Component Values—Si3036 Chipset 1 Component 2 C1, µ Elec/Tant, ±20% C6,C10,C16 C9,C28,C29 C11 3 C12 C7,C8,C13,C14,C18, C19,C20,C22 3 0.1 µ Elec/Tant/X7R, ±20% C23 2,4 C24,C25,C31,C32 5 C30 6 ...
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Analog Output Figure 20 illustrates an optional application circuit to support the analog output capability of the Si3038 for call progress monitoring purposes. The AOUT level can be set to 0 dB, –6 dB, –12 dB, and mute for both ...
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Si3038 Functional Description The Si3038 is an integrated chipset that provides a low- cost, isolated, silicon-based MC’97-compliant interface to the telephone line. The Si3038 complies with the AC’97 2.1 specification and requires only a few low-cost discrete components to achieve ...
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Table 19. Country Specific Register Settings (Continued) Register Country OHS Greece Guam Hong Kong Hungary Iceland India Indonesia Ireland Israel Italy 1 Japan 1 Jordan 1 Kazakhstan Kuwait Latvia Lebanon Luxembourg Macao 1,3 Malaysia Malta Mexico Morocco Netherlands New Zealand ...
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Si3038 Table 19. Country Specific Register Settings (Continued) Register Country Slovakia Slovenia South Africa South Korea Spain Sweden Switzerland 1 Syria 1 Taiwan 1 Thailand UAE United Kingdom USA Yemen Note: 1. See "DC Termination Considerations" on page 24 for ...
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As shown in Figure 19 on page 16, the C1, C2, C4, C24, and C25 capacitors isolate the Si3024 (system-side) from the Si3014 (line-side). All transmit, receive, control, ring detect, and caller ID data are ...
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Si3038 CTR21 DCT Mode .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 Loop Current (A) Figure 23. CTR21 Mode I/V Characteristics DC Termination Considerations Under certain line conditions, it ...
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The length of this count (in seconds) is 65536 divided by the sample rate. The GPIO1(GPIO11) bit will also be reset to zero by an off-hook event. When RFWE is 1, the GPIO1(GPIO11) bit will toggle active low when ...
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Si3038 GPIO Pin Status register. The Si3038 can also be programmed to wake up on events due to GPIO_A and GPIO_B. DTMF Dialing In CTR21 dc termination mode, the DIAL bit in register 62h should be set during DTMF dialing ...
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Power Down Fram e SYNC BIT_CLK SDATA_OUT slot 12 W rite to TAG prev. frame 56th s lot 12 SDATA_IN TAG prev. fram e Figure 24. AC-Link Power-Down/Up Sequence Although the DAA will remain off-hook during a billing tone event, ...
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Si3038 On-Hook Line Monitor The Si3038 allows the user to receive line activity when in an on-hook state. The LINE1_CID/LINE2_CID bit in slot 12 enables a low-power ADC which digitizes the signal passed across the RNG1/2 pins. This signal is ...
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The LCS value is a rough approximation of the loop current, and the designer is advised to use this value in a relative means rather than an absolute value. This feature enables the modem to determine ...
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Si3038 SDATA_IN) to the transmit pin, which is looped externally to the receive pin. To enable external analog loopback, set L1B2:0 (L2B2:0) = 110. Both analog loopback modes require power, which is typically supplied by the loop current from TIP ...
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Digital AC'97 Controller Figure 27. Si3038 Connection To AC’97 Controller (Primary Device Configuration) AC-Link Digital Serial Interface Protocol The Si3024 incorporates a 5-pin digital serial interface that links it to the AC’97 controller. AC-link is a bi- directional, fixed rate, ...
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Si3038 Tag Phase SYNC 12.228 MHz 81.4 nS BIT_CLK Valid SDATA_OUT slot(1) slot(2) Frame End of previous Time Slot "Valid" Audio Frame Bits ("1" = Time slot contains valid PCM data) Figure 29. AC-Link Audio Output Frame The AC-link protocol ...
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SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits (bit SDATA_IN Slot 1) to set active (low). SLOTREQ bits asserted during the current audio input frame signal ...
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Si3038 GPIO Name GPIO15 LINE2_GPIO_B GPIO14 LINE2_GPIO_A GPIO13 LINE2_DLCS GPIO12 LINE2_CID GPIO11 LINE2_RI GPIO10 LINE2_OH GPIO9:6 Reserved GPIO5 LINE1_GPIO_B GPIO4 LINE1_GPIO_A GPIO3 LINE1_DLCS GPIO2 LINE1_CID GPIO1 LINE1_RI GPIO0 LINE1_OH Vendor Optional Bit 3 Reserved Bit 2 LINE2_FDT Bit 1 LINE1_FDT ...
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Ready bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK and subsequently sampled by the AC’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points ...
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Si3038 Codec Register Access Whenever the AC’97 Digital Controller addresses the Si3024 as a primary codec or the codec responds to a read command, Slot 0 Tag bits should always be set to indicate actual valid data in Slot 1 ...
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Table 25. Secondary Codec Register Access Slot 0 Bit Definitions Bit 15 Frame Valid 14 Slot 1: Valid Command Address bit (Primary Codec only) 13 Slot 2: Valid Command Data bit (Primary Codec only) 12–3 Slot 3: 12 Valid bits ...
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Si3038 Control Registers Note: Any register not listed here is reserved and should not be written. Undefined/unimplemented registers return 0. Register Name D15 D14 D13 D12 D11 D10 3Ch Extended ID1 ID0 Modem ID 3Eh Extended PRF Modem Sta- tus ...
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Register 3Ch Extended Modem ID D15 D14 D13 D12 D11 ID1 ID0 Reset settings (dependent on pins ID1 and ID0) = 0001 Bit Name 15 ID1 ID1, ID0 is a 2-bit field which indicates the Codec configuration: Primary is 00; ...
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Si3038 Register 3Eh Extended Modem Status and Control D15 D14 D13 D12 D11 PRF PRE PRD Reset settings = 0xFF00 Bits 7–0 are read only, 1 indicates modem AFE subsystem readiness. Bits 13–8 are read/write and control modem AFE subsystem ...
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Register 40h Line 1 DAC/ADC Rate D15 D14 D13 D12 D11 SR15 SR14 SR13 SR12 SR11 SR10 Reset settings = 0x0000 Each DAC/ADC pair is governed by a read/write modem sample rate control register that contains a 16-bit unsigned value ...
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Si3038 Register 46h Line 1 DAC/ADC Level D15 D14 D13 D12 D11 Mute DAC3 DAC2 DAC1 Reset setting for Line 1 device = 0x8080 Reset setting for Line 2 device = 0x0000 This read/write register controls the modem AFE DAC ...
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Register 48h Line 2 DAC/ADC Level D15 D14 D13 D12 D11 Mute DAC3 DAC2 DAC1 Reset setting for Line 1 device = 0x0000 Reset setting for Line 2 device = 0x8080 This read/write register controls the modem AFE DAC and ...
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Si3038 Register 4Eh GPIO Pin Polarity and Type D15 D14 D13 D12 D11 GP15 GP14 GP13 GP12 GP11 GP10 Reset settings = 0xFFFF The GPIO Pin Polarity/Type register is read/write for selecting the polarity and type for Slot 12 I/O. ...
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Register 54h GPIO Pin Status D15 D14 D13 D12 D11 GI15 GI14 GI13 GI12 GI11 Reset settings = 0xxxxx GPIO Status is a read/write register that reflects the state of all GPIO pins (inputs and outputs) on slot 12. The ...
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Si3038 Register 56h Miscellaneous Modem AFE Status and Control D15 D14 D13 D12 D11 MLNK Reset settings = 0x0000 This read/write register defines the loopback modes available for the modem line ADCs/DACs. The default value after cold register reset (0xx000) ...
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Register 5Ah Chip ID and Revision D15 D14 D13 D12 D11 D10 D9 Reset settings = n/a Bit Name 15:9 Reserved Read returns zero. 8 CBID Chip B (line side) ID Line-side is domestic Line-side has ...
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Si3038 Register 5Ch Line Side Configuration 1 D15 D14 D13 D12 D11 ARM1 ARM0 ATM1 ATM0 IIRE Reset settings = 0xF010 Bit Name 15:14 ARM[1:0] Analog (Call Progress) Receive Path Mute dB –6 dB. 10 ...
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Bit Name 5 ACT AC Termination Select Selects the real impedance Selects the complex impedance. 4:3 DCT[1:0] DC Termination Select Reserved Japan Mode. Low voltage mode. (Transmit level = –3 dBm). 10 ...
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Si3038 Register 5Eh Line Side Status D15 D14 D13 D12 D11 D10 PDC Reset setting = 0x0000 Bit Name 15:11 Reserved Read returns zero. 10 PDC Charge Pump Disable. This bit disables the internal charge pump when set. 9 ROV ...
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Register 62h Line Side Configuration 2 D15 D14 D13 D12 D11 D10 Reset setting = 0x0000 Bit Name 15:9 Reserved Read returns zero. 8 DIAL DTMF Dialing Mode. This bit should be set during DTMF dialing in CTR21 mode if ...
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Si3038 Register 64h Line Side Configuration 3 D15 D14 D13 D12 D11 Reset setting = 0x0000 Bit Name 15:8 Reserved Read returns zero. 7 Reserved Read returns zero or one. 6:3 Reserved Read returns zero. 2 OVL Overload Detected. This ...
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A A— UL1 950 Designs using the Si3038 pass all overcurrent and over- voltage tests for UL1950 3rd Edition compliance with a couple of considerations. Figure 34 shows the designs that can ...
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Si3038 A B—CISPR22 Various countries are expected to adopt the IEC CISPR22 standard over the next few years. For example, the European Union (EU) has adopted a standard entitled EN55022, which is ...
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Pin Descriptions: Si3024 Si3024 (SOIC) MCLK/XIN 1 XOUT 2 BIT_CLK SDA TA _IN 5 SDA TA _OUT RESET SOIC TSSOP Pin Name Pin # Pin # 1 13 MCLK/XIN 2 14 ...
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Si3038 Table 28. 3024 Pin Descriptions (Continued) SOIC TSSOP Pin Name Pin # Pin # ID1 15 11 GPIO_B 16 12 GPIO_A 56 Description Analog Supply Voltage. Provides the analog supply voltage for the ...
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Pin Descriptions—Si3014 Pin # Pin Name 1 QE2 Transistor Emitter 2. Connects to the emitter of Q4. 2 DCT DC Termination. Provides dc termination to the telephone network. 3 IGND Isolated Ground. Connects to ground on the line-side interface. Also ...
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Si3038 Table 29. 3014 Pin Descriptions (Continued) Pin # Pin Name 14 RX Receive Input. Serves as the receive side input from the telephone network. 15 FILT Filter. Provides filtering for the dc termination circuits. 16 FILT2 Filter 2. Provides ...
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... Si3021-KS Si3014-KS Si3021-KT Si3021-KS Si3012-KS Si3021-KT Si3024-KS Si3012-KS Si3024-KT Si3024-KS Si3014-KS Si3024-KT Si3021-KS Si3015-KS Si3021-BS Si3015-BS Si3025-KS Si3012-KS Si3025-KS Si3014-KS Rev. 2.01 Si3038 Line Temperature (TSSOP) Si3014-KT 0°C to 70°C Si3012-KT 0°C to 70°C Si3012-KT 0°C to 70°C Si3014-KT 0° ...
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Si3038 SOIC Outline Figure 36 illustrates the package details for the Si3024 and Si3014. Table 31 lists the values for the dimensions shown in the illustration Seating Plane Figure 36. 16-pin Small Outline ...
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TSSOP Outline Figure 37 illustrates the package details for the Si3024 and Si3014. Table 32 lists the values for the dimensions shown in the illustration Figure 37. 16-pin Thin Small Shrink Outline Package (TSSOP) Table 32. ...
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Si3038 Rev 1.0 to Rev 1.1 Change List Typical Application Circuit was updated. C24, C25 value changed from 470 pF to 1000 pF and C31, C32 were added in Table 16 and Table 17. In Table 17, the tolerance was ...
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Rev. 2.01 Si3038 63 ...
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