AD9949KCPZ Analog Devices Inc, AD9949KCPZ Datasheet
AD9949KCPZ
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AD9949KCPZ Summary of contents
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FEATURES New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS pixel gain amplifier (PxGA® 10-bit variable gain amplifier (VGA) 12-bit, 36 MSPS analog-to-digital converter (ADC) Black ...
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AD9949 TABLE OF CONTENTS Specifications..................................................................................... 3 General Specifications ................................................................. 3 Digital Specifications ................................................................... 3 Analog Specifications................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... ...
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SPECIFICATIONS GENERAL SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD ( Drivers) RGVDD (RG Driver) DRVDD (D0 to D11 Drivers) DVDD (All Other Digital) POWER DISSIPATION ...
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AD9949 ANALOG SPECIFICATIONS AVDD = DVDD = 3 MIN MAX Table 3. Parameter CDS Gain 1 Allowable CCD Reset Transient Maximum Input Range before Saturation Maximum CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (P×GA) ...
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TIMING SPECIFICATIONS pF MHz, unless otherwise noted. L CLI Table 4. Parameter MASTER CLOCK (CLI) (See Figure 16) CLI Clock Period CLI High/Low Pulse Width Delay from CLI to Internal Pixel Period Position CLPOB ...
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AD9949 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect to AVDD and TCVDD AVSS HVDD and RGVDD HVSS, RGVSS DVDD and DRVDD DVSS, DRVSS Any VSS Any VSS Digital Outputs DRVSS CLPOB/PBLK and HBLK DVSS SCK, SL, and SDATA DVSS ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic Type DRVSS P 6 DRVDD D11 ...
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AD9949 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution ...
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EQUIVALENT INPUT/OUTPUT CIRCUITS AVDD R AVSS Figure 3. CCDIN (Pin 27) AVDD 330Ω 25kΩ CLI + 1.4V AVSS Figure 4. CLI (Pin 25) DVSS DATA THREE-STATE DVSS Figure 5. Data Outputs D0 to D11 (Pins ...
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AD9949 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.5 0 –0.5 –1.0 0 500 1000 1500 2000 2500 ADC OUTPUT CODE Figure 8. Typical DNL 200 400 600 VGA GAIN CODE (LSB) Figure 9. Output ...
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SYSTEM OVERVIEW V-DRIVER V1 TO Vx, VSG1 TO VSGx, SUBCK H1 TO H4, RG CCDIN CCD AD9949 INTEGRATED AFE + TD SERIAL INTERFACE Figure 11. Typical Application Figure 11 shows the typical system application diagram for the AD9949. The CCD ...
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AD9949 SERIAL INTERFACE TIMING The AD9949’s internal registers are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit data-word are written starting with the LSB. To ...
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COMPLETE REGISTER LISTING 1. All addresses and default values are expressed in hexadecimal. 2. All registers are VD/HD updated as shown in Figure 14, except for the registers indicated in Table 7, which are SL updated. Table 7. SL Updated ...
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AD9949 Table 8. AFE Register Map Data Bit Address Content Default Value 00 [11: [9: [7: [11: [17: [17:0] 0 Table 9. Miscellaneous Register Map Data Bit Address Content Default ...
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Table 10. CLPOB Register Map Data Bit Default Value Address Content (Hex) 20 [3: [23:0] FFFFFF 22 [23:0] FFFFFF 23 [23:0] FFFFFF 24 [23:0] FFFFFF 0 25 [7: [11:0] FFF 27 [11:0] FFF 28 [11:0] FFF ...
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AD9949 Table 12. HBLK Register Map Data Bit Default Value Address Content (Hex [3: [23:0] FFFFFF 45 [23:0] FFFFFF 46 [23:0] FFFFFF 47 [23:0] FFFFFF 48 [23:0] FFFFFF ...
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Table 14. AFE Operation Register Detail Data Bit Default Address Content Value 00 [1:0] 0 [2] 1 [3] 0 [4] 0 [5] 0 [7:6] 0 [8] 0 [9] 0 [11:10] 0 Table 15. AFE Control Register Detail Data Bit Default ...
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AD9949 PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9949 generates flexible high speed timing signals using the Precision Timing core. This core is the foundation for gener- ating the timing used for both the CCD and the AFE: the reset ...
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Table 16. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters Parameter Length Range Polarity 1b High/Low Positive Edge Edge Location Negative Edge Edge Location Sample Location Sample Location Drive ...
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AD9949 P[0] CLI 1 PIXEL PERIOD DOUT NOTES 1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS. CLI ...
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HORIZONTAL CLAMPING AND BLANKING The AD9949’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the ...
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AD9949 HD HBL K H1/H3 H1/H3 H2/H4 HBLK H1/H3 H2/H4 SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS. Table 20. Horizontal Sequence Control Parameters for CLPOB, PBLK, and HBLK Register Length Range SCP 12b 0 to 4095 Line ...
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GENERATING SPECIAL HBLK PATTERNS Six toggle positions are available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions may be used to generate special HBLK patterns, as ...
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AD9949 H-COUNTER SYNCHRONIZATION The H-Counter reset occurs seven CLI cycles following the HD falling edge. The PxGA steering is synchronized with the reset of the internal H-Counter (see Figure 26). As mentioned in the H-Counter Behavior section, the AD9949 H-counter ...
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POWER-UP PROCEDURE RECOMMENDED POWER-UP SEQUENCE When the AD9949 is powered up, the following sequence is recommended (refer to Figure 27 for each step): 1. Turn on the power supplies for the AD9949. 2. Apply the master clock input, CLI, VD, ...
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AD9949 ANALOG FRONT END DESCRIPTION AND OPERATION The AD9949 signal processing chain is shown in Figure 28. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. DC RESTORE To reduce the large ...
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VD COLOR PxGA STEERING 3 HD STEERING MODE SELECTION CONTROL SHP/SHD 2 GAIN0 GAIN1 4:1 PxGA GAIN 4:1 MUX REGISTERS MUX GAIN2 GAIN3 8 CDS PxGA VGA Figure 29. PxGA Block Diagram CCD: PROGRESSIVE BAYER COLOR STEERING MODE: PROGRESSIVE R ...
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AD9949 FIELDVAL FIELDVAL = PxGA GAIN REGISTER NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE FALLING EDGES WILL ALTERNATE THE PxGA GAIN ...
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The PxGA gain for each of the four channels is variable from 512 steps, specified using the PxGA GAIN01 and PxGA GAIN23 registers. The PxGA gain curve is shown in Figure 36. The PxGA ...
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AD9949 APPLICATIONS INFORMATION CIRCUIT CONFIGURATION The AD9949 recommended circuit configuration is shown in Figure 38. Achieving good image quality from the AD9949 requires careful attention to PCB layout. All signals should be routed to maintain low noise performance. The CCD ...
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DRIVING THE CLI INPUT The AD9949’s master clock input (CLI) may be used in two different configurations, depending on the application. Figure 41 shows a typical dc-coupled input from the master clock source. When the dc-coupled technique is used, the ...
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AD9949 PIXELS 28 DUMMY PIXELS SEQUENCE 1: VERTICAL BLANKING VERTICAL SHIFT CCDIN INVALID PIX SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB SEQUENCE 2: VERTICAL OPTICAL BLACK LINES OPTICAL BLACK VERTICAL SHIFT CCDIN SHP SHD H1/H3 H2/H4 HBLK ...
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SEQUENCE 3: EFFECTIVE PIXEL LINES OPTICAL BLACK CCDIN VERTICAL SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB OB DUMMY EFFECTIVE PIXELS Figure 46. Horizontal Sequences During Effective Pixels Rev Page AD9949 OPTICAL BLACK VERT SHIFT ...
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... ORDERING GUIDE Model Temperature Range AD9949KCP −20°C to +85°C AD9949KCPRL −20°C to +85°C 1 AD9949KCPZ −20°C to +85°C 1 AD9949KCPZRL −20°C to +85° AD9949AKCPZ −20°C to +85° AD9949AKCPZRL −20°C to +85° PB-free part. 2 The AD9949A is recommended for new designs and supports CCD line lengths > 4096 pixels. ...
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NOTES Rev Page AD9949 ...
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AD9949 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. D03751–0–11/04(B) Rev Page ...