DS90UR241IVS/NOPB National Semiconductor, DS90UR241IVS/NOPB Datasheet

IC SER/DESER 5-43MHZ 24B 48-TQFP

DS90UR241IVS/NOPB

Manufacturer Part Number
DS90UR241IVS/NOPB
Description
IC SER/DESER 5-43MHZ 24B 48-TQFP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS90UR241IVS/NOPB

Function
Serializer/Deserializer
Data Rate
1.03Gbps
Input Type
LVCMOS
Output Type
LVDS
Number Of Inputs
1
Number Of Outputs
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-TQFP, 48-VQFP
For Use With
SERDESUR-43USB - BOARD EVAL DS90UR124,DS90UR241
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*DS90UR241IVS/NOPB
DS90UR241IVSCT
DS90UR241IVSCT

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Price
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DS90UR241IVS/NOPB
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NS
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960
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© 2009 National Semiconductor Corporation
5-43 MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control FPD-Link II LVDS serial
stream with embedded clock information. This chipset is ide-
ally suited for driving graphical data to displays requiring 18-
bit color depth - RGB666 + HS, VS, DE + 3 additional general
purpose data channels. This single serial stream simplifies
transferring a 24-bit bus over PCB traces and cable by elim-
inating the skew problems between parallel data and clock
paths. It saves system cost by narrowing data paths that in
turn reduce PCB layers, cable width, and connector size and
pins.
The DS90UR241/124 incorporates FPD-Link II LVDS signal-
ing on the high-speed I/O. FPD-Link II LVDS provides a low
power and low noise environment for reliably transferring data
over a serial transmission path. By optimizing the Serializer
output edge rate for the operating frequency range EMI is fur-
ther reduced.
In addition, the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary
random lock, the Serializer’s parallel data are randomized to
the Deserializer without the need of REFCLK.
Features
Applications Diagram
TRI-STATE
Supports displays with 18-bit color depth
5MHz to 43MHz pixel clock
Automotive grade product AEC-Q100 grade 2 qualified
®
is a registered trademark of National Semiconductor Corporation.
201945
DS90UR241Q
DS90UR124Q
Applications
24:1 interface compression
Embedded clock with DC Balancing supports AC-coupled
data transmission
Capable to drive up to 10 meters shielded twisted-pair
cable
No reference clock required (deserializer)
Meets ISO 10605 ESD - Greater than 8 kV HBM ESD
structure
Hot plug support
EMI Reduction - Serializer accepts spread spectrum input;
data randomization and shuffling on serial link;
Deserializer provides Adjustable PTO (progressive turn-
on) LVCMOS outputs
@Speed BIST (built-in self test) to validate LVDS
transmission path
Individual power-down controls for both Transmitter and
Receiver
Power supply range 3.3V ± 10%
48-pin TQFP package for Transmitter and 64-pin TQFP
package for Receiver
Temperature range -40°C to +105°C
Backward compatible mode with DS90C241/DS90C124
Automotive Central Information Display
Automotive Instrument Cluster Display
Automotive Heads-Up Display
Remote Camera-based Driver Assistance Systems
September 4, 2009
20194527
www.national.com

Related parts for DS90UR241IVS/NOPB

DS90UR241IVS/NOPB Summary of contents

Page 1

... Supports displays with 18-bit color depth ■ 5MHz to 43MHz pixel clock ■ Automotive grade product AEC-Q100 grade 2 qualified Applications Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation DS90UR241Q DS90UR124Q ■ 24:1 interface compression ■ Embedded clock with DC Balancing supports AC-coupled data transmission ■ ...

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Block Diagram Ordering Information NSID Package Type DS90UR241QVS 48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch DS90UR241QVSX 48-Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch DS90UR241IVS 48-Lead TQFP style, 7.0 X 7.0 ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input Voltage LVCMOS Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration ...

Page 4

Symbol Parameter LVDS DC SPECIFICATIONS V Differential Threshold High TH Voltage V Differential Threshold Low TL Voltage I Input Current IN V Output Differential Voltage OD (D )–(D ) OUT+ OUT− ΔV Output Differential Voltage OD Unbalance V Offset Voltage ...

Page 5

Serializer Input Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Transmit Clock Period TCP t Transmit Clock High Time TCIH t Transmit Clock Low Time TCIL t TCLK Input Transition Time ...

Page 6

Symbol Parameter t R (0:7) Setup Data to ROS OUT RCLK (Group (0:7) Hold Data to RCLK ROH OUT (Group (8:15) Setup Data to ROS OUT RCLK (Group (8:15) Hold Data ...

Page 7

Note 11: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency. Note 12: Figures 1, 2 Figures 8, 12, 14show a falling edge data strobe (TCLK IN/RCLK OUT). Note 13: Figures 5, ...

Page 8

FIGURE 4. Serializer Input Clock Transition Times FIGURE 6. Serializer TRI-STATE Test Circuit and Delay www.national.com 20194506 FIGURE 5. Serializer Setup/Hold Times 8 20194507 20194508 ...

Page 9

FIGURE 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays FIGURE 8. Serializer Delay FIGURE 9. Transmitter Output Eye Opening (TxOUT_E_O) 9 20194509 20194510 20194515 www.national.com ...

Page 10

VOD = (D ) – OUT+ OUT− Differential output signal is shown as (D OUT+ FIGURE 11. Deserializer LVCMOS Output Load and Transition Times www.national.com ) – device in Data Transfer mode. OUT− FIGURE 10. Serializer ...

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FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay 11 20194513 20194514 www.national.com ...

Page 12

FIGURE 15. Deserializer Setup and Hold Times and PTO, PTOSEL = H Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI) Group 2 will be latched internally by sequence of (late 1UI, ...

Page 13

RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal. RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal. FIGURE 17. Receiver Input Tolerance (RxIN_TOL) and Sampling ...

Page 14

Pin # Pin Name I/O/PWR CONTROL AND CONFIGURATION PINS 9 TPWDNB LVCMOS_I 24 VODSEL LVCMOS_I 18 DEN LVCMOS_I 23 PRE LVCMOS_I 11 TRFB LVCMOS_I 12 RAOFF LVCMOS_I 5, 8, RES0 LVCMOS_I 13 LVDS SERIAL INTERFACE PINS 20 D LVDS_O OUT+ ...

Page 15

DS90UR124 Pin Diagram DS90UR124 Deserializer Pin Descriptions Pin # Pin Name I/O/PWR LVCMOS PARALLEL INTERFACE PINS 35-38, R [7:0] LVCMOS_O OUT 41-44 19-22, R [15:8] LVCMOS_O OUT 27-30 7-10, R [23:16] LVCMOS_O OUT 13-16 24 RCLK LVCMOS_O CONTROL AND CONFIGURATION ...

Page 16

Pin # Pin Name I/O/PWR 49 PTOSEL LVCMOS_I 63 RAOFF LVCMOS_I 64 SLEW LVCMOS_I 23 LOCK LVCMOS_O 50 RES0 LVCMOS_I 1-6, RES0 NC 17, 18, 33, 34 BIST MODE PINS(See Applications Informations section for more details.) 61 BISTEN LVCMOS_I 62 ...

Page 17

Functional Description The DS90UR241 Serializer and DS90UR124 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 1.03 Gbps throughput. The DS90UR241 transforms a ...

Page 18

RESYNCHRONIZATION If the Deserializer loses lock, it will automatically try to re-es- tablish lock. For example, if the embedded clock edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The ...

Page 19

Ratio the resistor values to bias the center point at 1.8V. For example (see V =3.3V, Rpullup=1KΩ, Rpulldown=1.2KΩ; DD Rpullup=100Ω, Rpulldown= 120Ω (strongest). The smaller values will consume more bias current, but will provide en- ...

Page 20

FIGURE 18. DS90UR241 Typical Application Connection POWER CONSIDERATIONS An all LVCMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the constant current source nature of the LVDS outputs minimize the slope of the speed vs. ...

Page 21

FIGURE 19. DS90UR124 Typical Application Connection PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS SERDES de- vices should be designed to provide low-noise power feed to the device. Good layout practice will also separate ...

Page 22

Connecting power or ground pins to an external bypass capacitor will increase the inductance of ...

Page 23

Truth Tables TPWDNB DEN (Pin 9) (Pin 18 FIGURE 22. Receiver Termination Option 2 FIGURE 23. Receiver Termination Option 3 TABLE 1. DS90UR241 Serializer Truth Table RAOFF Tx PLL Status ...

Page 24

RPWDNB REN (Pin 48) (Pin 60 www.national.com TABLE 2. DS90UR124 Deserializer Truth Table RAOFF Rx PLL Status ROUTn and RCLK (Pin 63) (Internal) (See Pin Diagram ...

Page 25

Physical Dimensions inches (millimeters) unless otherwise noted Dimensions show in millimeters only NS Package Number VBC48A Dimensions show in millimeters only NS Package Number VEC64A 25 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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