MAX3892ETH+ Maxim Integrated Products, MAX3892ETH+ Datasheet
MAX3892ETH+
Specifications of MAX3892ETH+
Related parts for MAX3892ETH+
MAX3892ETH+ Summary of contents
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... LVDS Parallel Clock and Data Inputs ♦ CML Serial Data and Clock Outputs ♦ Additional CML Output for System Loopback Testing Applications PART MAX3892EGH MAX3892ETH+ + Denotes a lead-free package. VCCVCO C Z 100Ω VCCVCO SDO+ PDI0+ ...
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SDH/SONET 4:1 Serializer with Clock Synthesis ABSOLUTE MAXIMUM RATINGS Supply Voltage V , VCCO, VCCVCO .....................-0.5V to +5V CC All Inputs and FIL .......................................-0. LVDS Output Voltage (PCLKO±)................-0. CML Output Current (SDO±, SCLKO±, SLBO±) ...
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SDH/SONET 4:1 DC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V -40°C to +85°C. Typical values are unless otherwise noted.) (Note 1) PARAMETER SYMBOL Differential Output Resistance Output Current Output Current CML ...
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SDH/SONET 4:1 Serializer with Clock Synthesis AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V -40°C to +85°C. Typical values are 50Ω ±1 +25°C, unless otherwise noted.) (Note 3) A ...
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SDH/SONET 4 +3.3V, CML loads AC-coupled to 50Ω ±1 SUPPLY CURRENT vs. TEMPERATURE 170 165 160 155 150 145 140 135 130 125 120 -40 - 100 TEMPERATURE (°C) ...
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SDH/SONET 4:1 Serializer with Clock Synthesis PIN NAME Negative System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock 9 SLBO- as shown in Table 1. Positive System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML ...
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SDH/SONET 4:1 Detailed Description The MAX3892 converts 4-bit-wide, 622Mbps/667Mbps data to 2.5Gbps/2.7Gbps serial data (Figure 2). Data is loaded into the 4:1 MUX through a 4 for wide tolerance to clock skew. Clock and data inputs are LVDS ...
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SDH/SONET 4:1 Serializer with Clock Synthesis Table 1. Loop-Back Operation Mode SLBPD SLBEN V X Power-Down SLBO Output IL 622MHz/667MHz Clock Output 2.5Gbps/2.7Gbps System Loop-Back Output Table 2. Setting the ...
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SDH/SONET 4:1 PDI[3..0]+ PDI[3..0]- PCLKI+ PCLKI- PCLKO+ PCLKO- RCLK+ RCLK- Figure 2. Functional Diagram V CC 50Ω 50Ω OUTPUT CIRCUIT Figure 3. Current-Mode Logic _______________________________________________________________________________________ Serializer with Clock Synthesis FIFOERROR RESET 4 D LVDS 4-BIT ...
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SDH/SONET 4:1 Serializer with Clock Synthesis SINGLE-ENDED OUTPUT (VPD+) - (VPD-) DIFFERENTIAL OUTPUT Figure 4. Differential Output Levels Pin Configuration TOP VIEW GND 1 VCCO 2 SCLKO- 3 SCLKO+ 4 VCCO 5 SDO- 6 MAX3892 SDO+ 7 VCCO ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2007 Maxim Integrated Products Serializer with Clock Synthesis is a registered trademark of Maxim Integrated Products, Inc ...