FIN1216MTDX Fairchild Semiconductor, FIN1216MTDX Datasheet

IC SERIALIZER/DESERIAL 48-TSSOP

FIN1216MTDX

Manufacturer Part Number
FIN1216MTDX
Description
IC SERIALIZER/DESERIAL 48-TSSOP
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FIN1216MTDX

Function
Serializer/Deserializer
Data Rate
1.785Gbps
Input Type
LVDS
Output Type
LVTTL
Number Of Inputs
3
Number Of Outputs
21
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FIN1216MTDX
FIN1216MTDXTR

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FIN1216MTDX
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Part Number:
FIN1216MTDX
Manufacturer:
FAIRCHILD
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© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
FIN1215 / FIN1216 / FIN1217/ FIN1218
LVDS 21-Bit Serializers / De-Serializers
Features
Ordering Information
Part Number
FIN1215MTDX
FIN1216MTDX
FIN1217MTDX
FIN1218MTDX
(Preliminary)
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Low Power Consumption
20MHz to 85MHz Shift Clock Support
50% Duty Cycle on the Clock Output of Receiver
±1V Common-mode Range ~1.2V
Narrow Bus Reduces Cable Size and Cost
High Throughput: 1.785Gbps
Up to 595Mbps per Channel
Internal PLL with No External Components
Compatible with TIA/EIA-644 Specification
Offered in 48-lead TSSOP Packages
Temperature
-40 to + 85°C
Operating
Range
Status
RoHS
Eco
48-Lead Thin Shrink Small Outline Package (TSSOP)
Description
The FIN1217 and FIN1215 transform 21-bit wide
parallel LVTTL (Low-Voltage TTL) data into three serial
LVDS
streams. A phase-locked transmit clock is transmitted in
parallel with the data stream over a separate LVDS link.
Every cycle of transmit clock, 21 bits of input LVTTL
data are sampled and transmitted.
The FIN1216 and FIN1218 receives and converts the
three serial LVDS data streams back into 21 bits of
LVTTL data. Table 1 provides a matrix summary of the
serializers
FIN1217, at a transmit clock frequency of 85MHz, 21
bits of LVTTL data are transmitted at a rate of 595Mbps
per LVDS channel.
These chipsets solve EMI and cable size problems
associated with wide and high-speed TTL interfaces.
Package
(Low-Voltage
and
de-serializers
Differential
available.
Signaling)
September 2009
Tape and Reel
Packing
www.fairchildsemi.com
Method
For
data
the

Related parts for FIN1216MTDX

FIN1216MTDX Summary of contents

Page 1

... Compatible with TIA/EIA-644 Specification Offered in 48-lead TSSOP Packages Ordering Information Operating Part Number Temperature Range FIN1215MTDX FIN1216MTDX - 85°C FIN1217MTDX FIN1218MTDX (Preliminary) For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 ...

Page 2

... Figure 1. FIN1217 / FIN1215 Transmitter Functional Diagram Figure 2. FIN1218 / FIN1216 Receiver Functional Diagram Table 1. Serializers / De-Serializers Chip Matrix CLK Part Frequency FIN1215 66 FIN1216 66 FIN1217 85 FIN1218 85 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 LVTTL IN LVDS OUT LVDS LVTTL Package OUT 48-Lead TSSOP ...

Page 3

... GND © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Figure 3. FIN1217 / FIN1215 (21:3 Transmitter) Description of Signals LVTTL Level Inputs LVTTL Level Clock Input; the rising edge is for data strobe Positive LVDS Differential Data Output Negative LVDS Differential Data Output ...

Page 4

... GND © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Figure 4. FIN1216 / FIN1218 (3:21 Receiver) Description of Signals Negative LVDS Differential Data Output Positive LVDS Differential Data Output Negative LVDS Differential Clock Output Positive LVDS Differential Clock Output LVTTL Level Data Outputs Goes HIGH for /PwrDn LOW LVTTL Level Clock Output LVTTL Level Input ...

Page 5

... Failsafe condition is defined as the input being terminated and un-driven, shorted, or open RxCLKIn± is removed prior to the RxIn± date being removed, RxOut is the last valid state. If RxIn± data is removed prior to RxCLKIn± being removed, RxOut is HIGH. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (1) PwrDn TxOut± ...

Page 6

... Note: 6. 100mV V noise should be tested for frequency at least up to 2MHz. All the specifications should be met under CC such a noise level. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Parameter LVDS I/O to Ground All Pins (FIN1215, FIN1217) FIN1215, FIN1217 Only ...

Page 7

... The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. 10. FIN1217 only. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 =3.3V; minimum and maximum are at over supply voltages and operating ...

Page 8

... TPPB3 t Transmitter Output Pulse Position of Bit 4 TPPB4 t Transmitter Output Pulse Position of Bit 5 TPPB5 t Transmitter Output Pulse Position of Bit 6 TPPB6 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Conditions Figure 10 10% to 90% Figure 11 Figure 8 Figure 10 f=85MHz FIN1217 only (11) ...

Page 9

... MSB is output from transmitter. 13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter of less than 2ns. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Conditions Min ...

Page 10

... The power supply current for the receiver can be different due to the number of active I/O channels. 15. 85MHz specification for FIN1218 only. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 =3.3V. Positive current values refer to the current flowing into device and ...

Page 11

... RSPB3 t Receiver Input Strobe Position of Bit 4 RSPB4 t Receiver Input Strobe Position of Bit 5 RSPB5 t Receiver Input Strobe Position of Bit 6 RSPB6 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Conditions Min. Typ. 10.0 11.0 Figure 12 10.0 12.2 Rising Edge Strobe 6 ...

Page 12

... Receiver Phase Lock Loop Set Time RPLLS Notes: 16. Total channel latency from serializer to deserializer 17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Conditions Figure 21 f=65MHz ...

Page 13

... Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages ( 1.25 1.15 2.40 2.30 0.10 0 1.50 0.90 2.40 1.80 0.60 0 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 <=1ns. F Resulting Differential Input Voltage (mV 1.15 1.25 2.30 2.40 0 0.10 0.90 1.50 1 ...

Page 14

... Figure 8. Transmitter LVDS Output Load and Transition Times Figure 9. Receiver LVTTL/CMOS Output Load and Transition Times Figure 10. Transmitter Set-up/Hold and HIGH/LOW Times (Rising Edge Strobe) Figure 11. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Figure 7. Worst-Case Test Pattern Transmitter Input Clock Transition Time 14 ...

Page 15

... AC Loadings and Waveforms Figure 12. Figure 13. Figure 14. Figure 15. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Receiver Set-up/Hold and HIGH/LOW Times Transmitter Clock-In to Clock-Out Delay (Rising Edge Strobe) Receiver Clock-In to Clock-Out Delay (Rising Edge Strobe) Transmitter Phase-Lock-Loop Set Time 15 www ...

Page 16

... Note: This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter. Figure 19. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Figure 16 ...

Page 17

... AC Loadings and Waveforms Figure 20. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued)] Transmitter Output Pulse Bit Position Figure 21. Receiver Strobe Bit Position 17 www.fairchildsemi.com ...

Page 18

... The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross V with 100mV noise (V © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 (Continued) Figure 22. ...

Page 19

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...

Page 20

... Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 20 www.fairchildsemi.com ...

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