ISL34341INZ-T13 Intersil, ISL34341INZ-T13 Datasheet

IC VIDEO SERDES LONG 64-EPTQFP

ISL34341INZ-T13

Manufacturer Part Number
ISL34341INZ-T13
Description
IC VIDEO SERDES LONG 64-EPTQFP
Manufacturer
Intersil
Datasheet

Specifications of ISL34341INZ-T13

Function
Serializer/Deserializer
Input Type
LVCMOS
Output Type
LVCMOS
Number Of Inputs
2
Number Of Outputs
2
Voltage - Supply
1.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL34341INZ-T13
Manufacturer:
Intersil
Quantity:
10 000
WSVGA 24-Bit Long-Reach Video
SERDES with Bi-directional Side-Channel
The ISL34341 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed
differential signal. This differential signal is converted back to
parallel video at the remote end by the deserializer. It also
transports auxiliary data bi-directionally over the same link
during the video vertical retrace interval.
I
devices on the remote side of the link. An I
be placed on either side of the link allowing bi-directional I
communication through the link to the external devices on
the other side. Both chips can be fully configured from a
single controller or independently by local controllers.
Ordering Information
ISL34341INZ* ISL34341INZ -40 to +85 64 Ld EPTQFP Q64.10x10C
*Add “-T13” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
2
C bus mastering allows the placement of external slave
NUMBER
(Note)
PART
S O U R C E
V ID E O
MARKING
24
PART
RG BA/B/C
VSYN C
HSYN C
DATAEN
PC LK _IN
®
3.3V
RANGE
TEMP.
(°C)
1
ISL34341
Data Sheet
1.8V
PACKAGE
(Pb-free)
VDD _IO
2
C controller can
SERIO P
SER IO N
VD D_IO
27nF
27nF
DWG. #
1-888-INTERSIL or 1-888-468-3774
PKG.
10m D IFFER EN TIAL CABLE
2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
C
REF_C LK
Features
• 24-bit RGB transport over single differential pair
• 6MHz to 40MHz pixel clock rates
• Bi-directional auxiliary data transport without extra
• I
• 40MHz PCLK transports
• Internal 100Ω termination on high-speed serial lines
• DC balanced with industry standard 8b/10b line code
• Hot plugging with automatic resynchronization every line
• 16 programmable settings each for transmitter amplitude
• Programmable power-down of the transmitter and the
• Same device for serializer and deserializer simplifies
• I
• 8kV ESD rating for serial lines
• Pb-free (RoHS compliant)
Applications
• Navigation and display systems
• Video entertainment systems
• Industrial computing terminals
• Remote cameras
bandwidth and over the same differential pair
controller on either the serializer or deserializer
- SVGA 800x600 @ 70fps, 16% blanking
- WSVGA 1024x600 @ 60fps, 8% blanking
allows AC-coupling
- Provides immunity against ground shifts
boost and pre-emphasis and receiver equalization allow
for longer cable lengths and higher data rates
receiver
inventory
2
2
C Bus Mastering to the remote side of the link with a
C communication interface
27nF
27nF
October 8, 2010
All other trademarks mentioned are the property of their respective owners.
PC LK _IN
SERIO P
SER IO N
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
3.3V
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
ISL34341
1.8V
VD D_IO
VDD _IO
PC LK _O UT
RG BA/B/C
D ATAEN
HSYNC
VSYNC
ISL34341
24
FN6827.1
V ID E O
S IN K

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ISL34341INZ-T13 Summary of contents

Page 1

... RANGE (Note) MARKING (°C) ISL34341INZ* ISL34341INZ - EPTQFP Q64.10x10C *Add “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, ...

Page 2

Pinout VIDEO_TX VDD_IO PCLK_OUT RGBA0 RGBA1 RGBA2 RGBA3 RGBA4 RGBA5 RGBA6 RGBA7 RGBB0 RGBB1 RGBB2 RGBB3 GND_IO Block Diagram SCL SDA RAM 3 V/H/DE TDM RGB 24 VIDEO_TX (HI) PCLK_IN (REF_CLK WHEN VIDEO_TX IS LO) PCLK_OUT 2 ...

Page 3

... Thermal Resistance (Typical, Notes 1, 2) EPTQFP Maximum Power Dissipation 327mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling A SYMBOL CONDITIONS I VIDEO_TX = 1 ...

Page 4

Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V VDD_TX = VDD_P = VDD_AN = 3.3V, T capacitor = 27nF. (Continued) PARAMETER POWER-DOWN SUPPLY CURRENT Total 1.8V Power-Down Supply Current Total 3.3V ...

Page 5

Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V VDD_TX = VDD_P = VDD_AN = 3.3V, T capacitor = 27nF. (Continued) PARAMETER HS Generated Output Common Mode Voltage HS Common Mode Serializer-Deserializer ...

Page 6

Pin Descriptions (Continued) PIN NUMBER PIN NAME 49 VIDEO_TX 29, 30 SCL, SDA I2CA[3:0] 35 MASTER 16 RSTB/PDB 14 STATUS 36 REF_RES 27 GND_P 48, 64 GND_IO 44, 45 GND_CDR 39, 42 GND_TX 37 GND_AN 17, 18 ...

Page 7

Diagrams VOD VIDEO_TX = 1 PCLK_IN t IS RGB[A:C][7:0] VALID DATA HSYNC VSYNC DATAEN FIGURE 2. PARALLEL VIDEO INPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg ISL34341 TR FIGURE 1. VOD vs TXCN SETTING 1/f ...

Page 8

VIDEO_TX = 0 PCLK_OUT t DV VALID DATA RGB[A:C][7:0] HSYNC VSYNC DATAEN FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg Applications Overview A pair of ISL34341 SERDES transports 24-bit parallel video (16-bit ...

Page 9

Power Supply Sequencing The 3.3V supply must be higher than the 1.8V supply at all times, including during power-up and power-down. To meet this requirement, the 3.3V supply must be powered up before the 1.8V supply. For the deserializer, REF_CLK ...

Page 10

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

Page 11

Thin Plastic Quad Flatpack Exposed Pad Plastic Packages (EPTQFP -D- EJECTOR PIN MARK NOT PIN # PIN 1 TOP VIEW 0.020 0.008 MIN o 0 MIN GAGE PLANE 0.25 ...

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