DS92LV1212TMSA National Semiconductor, DS92LV1212TMSA Datasheet
DS92LV1212TMSA
Specifications of DS92LV1212TMSA
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DS92LV1212TMSA Summary of contents
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... SYNC patterns. Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100982 Features n Clock recovery without SYNC patterns-random lock n Guaranteed transition every data transfer cycle < ...
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Block Diagram (Continued) Functional Description The DS92LV1212 is a 10-bit Deserializer chip designed to receive data over a heavily loaded differential backplanes at clock speeds from 16 MHz to 40 MHz. It may also be used to receive data over ...
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Random Lock Initialization and Resynchronization The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer, however, the DS92LV1212 can attain lock to a data stream without re- ...
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... RMT Patterns DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DIN8 Held Low-DIN9 Held High Creates an RMT Pattern NSID DS92LV1021TMSA DS92LV1212TMSA www.national.com DS100982-23 DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DS100982-25 Order Numbers Function Serializer Deserializer 4 DS100982-24 Package MSA28 MSA28 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage −0. CMOS/TTL Output Voltage −0. Bus LVDS Receiver Input Voltage Junction Temperature Storage Temperature Lead Temperature ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Receiver out Clock RCP Period t CMOS/TTL Low-to-High CLH Transition Time t CMOS/TTL High-to-Low CHL Transition Time t Deserializer Delay DD t ROUT (0-9) ...
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AC Timing Diagrams and Test Circuits FIGURE 1. “Worst Case” Deserializer ICC Test Pattern FIGURE 2. Deserializer CMOS/TTL Output Load and Transition Times FIGURE 3. Serializer Delay FIGURE 4. Deserializer Delay 7 DS100982-4 DS100982-6 DS100982-11 DS100982-12 www.national.com ...
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AC Timing Diagrams and Test Circuits Timing shown for RCLK_R/F = LOW Duty Cycle ( RDC FIGURE 5. Deserializer Setup and Hold Times FIGURE 6. Deserializer TRI-STATE Test Circuit and Timing www.national.com (Continued) DS100982-13 DS100982-14 8 ...
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AC Timing Diagrams and Test Circuits FIGURE 7. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays FIGURE 8. Deserializer PLL Lock Time from SyncPAT (Continued) 9 DS100982-15 DS100982-22 www.national.com ...
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AC Timing Diagrams and Test Circuits SW - Setup and Hold Time (Internal data sampling window Serializer Output Bit Position Jitter JIT t = Receiver Sampling Margin Time RSM FIGURE 9. Receiver Bus LVDS Input Skew Margin Application ...
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... In the point-to-point configuration the potential of offsetting the ground levels of the Serializer vs. the Deserial- izer must be considered. Bus LVDS provides a plus / minus one volt common mode range at the receiver inputs. DS100982-26 DS92LV1212TMSA - Deserializer DS100982-19 No. Description ± 15–19, Data Output ...
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Deserializer Pin Description Pin Name I/O RCLK_R/F I RI+ I RI− I PWRDN I LOCK O RCLK O REN I DVCC I DGND I AVCC I AGND I REFCLK I Truth Table RI RI− RCLK_R ...
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... Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS92LV1021TMSA or DS92LV1212TMSA LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1 ...