NJU3716L NJR, NJU3716L Datasheet - Page 3

IC 16BIT SRL TO PRL CONVTR24SDIP

NJU3716L

Manufacturer Part Number
NJU3716L
Description
IC 16BIT SRL TO PRL CONVTR24SDIP
Manufacturer
NJR
Datasheet

Specifications of NJU3716L

Function
Serial to Parallel
Input Type
Serial
Output Type
Parallel
Number Of Inputs
4
Number Of Outputs
16
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-25°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-SDIP (0.300", 7.62mm)
Operating Supply Voltage
4.5 V to 5.5 V
Logic Type
Serial to Parallel Data Converter
Maximum Operating Frequency
5 MHz
Maximum Operating Temperature
+ 85 C
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 25 C
Mounting Style
SMD/SMT
Operating Current
0.1 mA
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NJU3716L
Manufacturer:
JRC
Quantity:
45
Part Number:
NJU3716L
Manufacturer:
NJR
Quantity:
1 000
Part Number:
NJU3716L
Manufacturer:
NJR Corporation/NJRC
Quantity:
243
(1) Reset
(2) Data Transmission
(3) Cascade Connection
Ver.2003-11-18
Note 1)
FUNCTIONAL DESCRIPTION
output are "L" level.
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
latches.
the clock signal should be controlled for data order.
unrelated with the CLR and STB status.
to protect the noise.
CLK
H
X
L
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
Normally, the CLR terminal should be "H" level.
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore,
The serial data input from DATA terminal is output from the SO terminal through internal shift register
Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure
X: Don’t care
STB
H
X
L
CLR
H
H
L
All of latches are reset (the data in the shift register is no change).
All of parallel conversion outputs are "L".
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift register.
The serial data into the DATA terminal are inputted to the shift register.
In this stage, the data in the latch is not changed.
OPERATION
NJU3555
NJU3555
NJU3716
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