PCA9517AD,112 NXP Semiconductors, PCA9517AD,112 Datasheet

IC I2C BUS REPEATER 8-SOIC

PCA9517AD,112

Manufacturer Part Number
PCA9517AD,112
Description
IC I2C BUS REPEATER 8-SOIC
Manufacturer
NXP Semiconductors
Type
Repeaterr
Datasheet

Specifications of PCA9517AD,112

Tx/rx Type
I²C Logic
Delay Time
170ns
Capacitance - Input
6pF
Voltage - Supply
2.7 V ~ 5.5 V
Current - Supply
5mA
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935285763112
PCA9517AD
PCA9517AD

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9517AD,112
Manufacturer:
NXP
Quantity:
12 000
1. General description
The PCA9517A is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I
While retaining all the operating modes and features of the I
level shifts, it also permits extension of the I
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using
the PCA9517A enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are overvoltage tolerant and are
high-impedance when the PCA9517A is unpowered.
The 2.7 V to 5.5 V bus port B drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus port A drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V
LOW on the port A which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the port B PCA9517A I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517A (port B),
or PCA9518. Port A of two or more PCA9517As can be connected together, however, to
allow a star topography with port A on the common bus, and port A can be connected
directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517As can
be connected in series, port A to port B, with no build-up in offset voltage with only time of
flight delays to consider.
The PCA9517A drivers are not enabled unless V
2.5 V. The EN pin can also be used to turn the drivers on and off under system control.
Caution should be observed to only change the state of the enable pin when the bus is
idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This
prevents a lock-up condition from occurring. The output pull-down on port A drives a hard
LOW and the input level is set at 0.3V
LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
Table 1.
[1]
[2]
Parameter
electrostatic discharge, HBM
electrostatic discharge, MM
PCA9517A
Level translating I
Rev. 02 — 5 May 2008
Will continue to be supported for existing designs and new designs where migrating to the PCA9517A is not
possible.
Highly recommended for all new designs due to improved I
PCA9517 and PCA9517A comparison
2
C-bus repeater
CC(A)
to accommodate the need for a lower
2
PCA9517
> 2 kV
> 200 V
C-bus by providing bidirectional buffering for
CC(A)
2
C-bus operation and ESD performance.
[1]
is above 0.8 V and V
2
C-bus or SMBus applications.
2
C-bus system during the
Product data sheet
PCA9517A
> 5.5 kV
> 450 V
CC(B)
[2]
is above

Related parts for PCA9517AD,112

PCA9517AD,112 Summary of contents

Page 1

PCA9517A Level translating I Rev. 02 — 5 May 2008 1. General description The PCA9517A is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2 5 ...

Page 2

... NXP Semiconductors 2. Features I 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device I Voltage level translation from 0 5.5 V and from 2 5 Footprint and functional replacement for PCA9515/15A C-bus and SMBus compatible I Active HIGH repeater enable input I Open-drain input/outputs ...

Page 3

... NXP Semiconductors 4. Functional diagram Fig 1. 5. Pinning information 5.1 Pinning V Fig 2. 5.2 Pin description Table 3. Symbol V CC(A) SCLA SDAA GND EN SDAB SCLB V CC(B) PCA9517A_2 Product data sheet V CC(A) PCA9517A SDAA SCLA V CC(B) pull-up resistor EN Functional diagram of PCA9517A CC(A) CC(B) SCLA 2 7 SCLB ...

Page 4

... NXP Semiconductors 6. Functional description Refer to The PCA9517A enables I without degradation of system performance. The PCA9517A contains two bidirectional open-drain buffers specifically designed to support up-translation/down-translation between the low voltage (as low as 0.9 V) and a 3 and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (V ...

Page 5

... NXP Semiconductors 7. Application design-in information A typical application is shown 3 Master devices can be placed on either bus. Fig 4. The PCA9517A tolerant does not require any additional circuitry to translate between 0 5.5 V bus voltages and 2 5.5 V bus voltages. When port A of the PCA9517A is pulled LOW by a driver on the I detects the falling edge when it goes below 0 ...

Page 6

... NXP Semiconductors Fig SDAA SDA SCLA SCL BUS PCA9517A MASTER EN Fig 6. Typical series application PCA9517A_2 Product data sheet V CC( SDA SCL BUS MASTER Typical star application SDAB SDAA SDAB SCLB SCLA SCLB PCA9517A EN Rev. 02 — 5 May 2008 PCA9517A Level translating I V CC(B) ...

Page 7

... NXP Semiconductors Fig 7. SCL SDA Fig 8. SCL SDA Fig 9. PCA9517A_2 Product data sheet CARD 1 CARD Typical application of PCA9517A driving a short cable 9th clock pulse acknowledge Bus A (0 5.5 V bus) waveform 9th clock pulse acknowledge V of slave OL Bus B (2 5.5 V) waveform Rev. 02 — 5 May 2008 ...

Page 8

... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage port B CC(B) V supply voltage port A CC(A) V voltage on an input/output pin I/O I input/output current I/O I input current I P total power dissipation tot ...

Page 9

... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics 5.5 V; GND = Symbol Parameter Supplies V supply voltage port B CC(B) V supply voltage port A CC(A) I supply current on pin V CC(VCC(A)) I HIGH-level supply current CCH I LOW-level supply current CCL I contention port A supply current CC(A)c Input and output SDAB and SCLB ...

Page 10

... NXP Semiconductors Table 5. Static characteristics 5.5 V; GND = Symbol Parameter Enable V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level input current on IL(EN) pin EN I input leakage current LI C input capacitance i [1] LOW-level supply voltage. [2] V specification is for the first LOW level seen by the SDAB/SCLB lines SDAB/SCLB lines ...

Page 11

... NXP Semiconductors 10.1 AC waveforms input 1 PHL 80 % 0.6 V output THL Fig 10. Propagation delay and transition times; port B to port A Fig 12. Propagation delay 11. Test information Fig 13. Test circuit for open-drain outputs PCA9517A_2 Product data sheet 3.0 V 1 PLH 1 0 TLH 002aad642 Fig 11. Propagation delay and transition times; ...

Page 12

... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 15

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 16

... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 9. Acronym CDM CMOS ESD HBM 2 I C-bus MM RC SMBus PCA9517A_2 Product data sheet ...

Page 17

... NXP Semiconductors 15. Revision history Table 10. Revision history Document ID Release date PCA9517A_2 20080505 • Modifications: Table 1 “PCA9517 and PCA9517A – changed HBM for PCA9517A from “> 6.5 kV” to “>5.5 kV” – changed MM for PCA9517A from “> 550 V” to “> 450 V” ...

Page 18

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 19

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Enable 6.2 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Application design-in information . . . . . . . . . . 5 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 AC waveforms ...

Related keywords