PCA9517AD,118 NXP Semiconductors, PCA9517AD,118 Datasheet

IC I2C BUS REPEATER 8-SOIC

PCA9517AD,118

Manufacturer Part Number
PCA9517AD,118
Description
IC I2C BUS REPEATER 8-SOIC
Manufacturer
NXP Semiconductors
Type
Repeaterr
Datasheets

Specifications of PCA9517AD,118

Package / Case
8-SOIC (3.9mm Width)
Mounting Type
Surface Mount
Current - Supply
5mA
Voltage - Supply
2.7 V ~ 5.5 V
Delay Time
170ns
Capacitance - Input
6pF
Tx/rx Type
I²C Logic
Supply Voltage (max)
5.5 V
Supply Voltage (min)
0.9 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Circuits
Dual
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935285763118::PCA9517AD-T::PCA9517AD-T
1. General description
2. Features
The PCA9517 is a CMOS integrated circuit that provides level shifting between low
voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I
While retaining all the operating modes and features of the I
level shifts, it also permits extension of the I
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using
the PCA9517 enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are over voltage tolerant and are
high-impedance when the PCA9517 is unpowered.
The 2.7 V to 5.5 V bus B-side drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus A-side drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the B-side translating into a nearly 0 V
LOW on the A-side which accommodates smaller voltage swings of lower voltage logic.
The static offset design of the B-side PCA9517 I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B-side),
or PCA9518. The A-side of two or more PCA9517s can be connected together, however,
to allow a star topography with the A-side on the common bus, and the A-side can be
connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9517s can be connected in series, A-side to B-side, with no build-up in offset voltage
with only time of flight delays to consider.
The PCA9517 drivers are not enabled unless V
The EN pin can also be used to turn the drivers on and off under system control. Caution
should be observed to only change the state of the enable pin when the bus is idle.
The output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the A-side
drives a hard LOW and the input level is set at 0.3V
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
I
I
I
I
PCA9517
Level translating I
Rev. 03 — 30 January 2007
2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of
the device
Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
Footprint and functional replacement for PCA9515/15A
I
2
C-bus and SMBus compatible
2
C-bus repeater
2
C-bus by providing bidirectional buffering for
CCA
is above 0.8 V and V
CCA
to accommodate the need for a
2
C-bus or SMBus applications.
2
C-bus system during the
Product data sheet
CC
is above 2.5 V.

Related parts for PCA9517AD,118

PCA9517AD,118 Summary of contents

Page 1

PCA9517 Level translating I Rev. 03 — 30 January 2007 1. General description The PCA9517 is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2 5 ...

Page 2

... NXP Semiconductors I Active HIGH repeater enable input I Open-drain input/outputs I Lock-up free operation I Supports arbitration and clock stretching across the repeater I Accommodates Standard mode and Fast mode I I Powered-off high-impedance I I A-side operating supply voltage range B-side operating supply voltage range of 2 5.5 V ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for SO8 5.2 Pin description Table 2. Symbol V CCA SCLA SDAA GND EN SDAB SCLB V CCB 6. Functional description Refer to The PCA9517 enables I without degradation of system performance. The PCA9517 contains two bidirectional open-drain buffers specifically designed to support up-translation/down-translation between the low voltage (as low as 0 ...

Page 4

... NXP Semiconductors be able to rise to 0.5 V until the A-side rises above 0.3V to rise being pulled up by the external pull-up resistor. The V the 0.3V circuit. The PCA9517 logic and all I/Os are powered by the V 6.1 Enable The EN pin is active HIGH with an internal pull- when the repeater is active ...

Page 5

... NXP Semiconductors 7. Application design-in information A typical application is shown 3 Master devices can be placed on either bus. Fig 4. Typical application The PCA9517 tolerant does not require any additional circuitry to translate between 0 5.5 V bus voltages and 2 5.5 V bus voltages. When the A-side of the PCA9517 is pulled LOW by a driver on the I detects the falling edge when it goes below 0 ...

Page 6

... NXP Semiconductors Fig 5. Typical star application SDAA SDA SCLA SCL BUS PCA9517 MASTER EN Fig 6. Typical series application PCA9517_3 Product data sheet V CCA SDAA SDA SCLA SCL BUS MASTER EN SDAA SCLA EN SDAA SCLA SDAB SDAA SDAB SCLB SCLA SCLB PCA9517 EN Rev. 03 — 30 January 2007 ...

Page 7

... NXP Semiconductors Fig 7. Typical application of PCA9517 driving a short cable SCL SDA Fig 8. Bus A (0 5.5 V bus) waveform SCL SDA Fig 9. Bus B (2 5.5 V) waveform PCA9517_3 Product data sheet CARD 1 CARD 9th clock pulse acknowledge 9th clock pulse acknowledge V of slave OL Rev. 03 — 30 January 2007 ...

Page 8

... NXP Semiconductors 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage, B-side bus CCB V supply voltage, A-side bus CCA 2 V voltage on I C-bus B-side, or enable (EN) bus I DC current P total power dissipation tot ...

Page 9

... NXP Semiconductors 9. Static characteristics Table 4. Static characteristics 5.5 V; GND = Symbol Parameter Supplies V supply voltage, B-side bus CCB V supply voltage, A-side bus CCA I supply current on pin V CC(VCCA) I HIGH-state supply current CCH I LOW-state supply current CCL I quiescent supply current in CCAc contention Input and output SDAB and SCLB ...

Page 10

... NXP Semiconductors Table 4. Static characteristics 5.5 V; GND = Symbol Parameter Enable V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level input current on pin EN IL(EN) I input leakage current LI C input capacitance i [1] LOW-level supply voltage. [2] V specification is for the first LOW level seen by the SDAB/SCLB lines SDAB/SCLB lines ...

Page 11

... NXP Semiconductors 10.1 AC waveforms input 1 PHL 80 % 0.6 V output t(HL) Fig 10. Propagation delay and transition times; B-side to A-side Fig 12. Propagation delay 11. Test information Fig 13. Test circuit for open-drain outputs PCA9517_3 Product data sheet 3.0 V 1 PLH 1 0 t(LH) 002aac207 Fig 11. Propagation delay and transition times; ...

Page 12

... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 13

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 15

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 16

... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 8. Acronym CDM CMOS ESD HBM 2 I C-bus MM SMBus PCA9517_3 Product data sheet ...

Page 17

... Document ID Release date PCA9517_3 20070130 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 JESD22-A115” • ...

Page 18

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 19

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 6.1 Enable 6.2 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Application design-in information . . . . . . . . . . 5 8 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 AC waveforms ...

Related keywords