SLXT914QC.B3 Intel, SLXT914QC.B3 Datasheet - Page 19

• Manufacturer Part Number: SLXT914QC.B3
• Description: IC QUAD ETHERNET REPEATER 100QFP
• Manufacturer: Intel
• Type: Repeaterr

Specifications of SLXT914QC.B3

• Rohs Status: RoHS non-compliant
• Tx/rx Type: Ethernet
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 180mA
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Delay Time: -
• Capacitance - Input: -
• Other names: 831521

2.4.2
Datasheet
Table 9.
Table 10. Setup Register Bit Definitions
Setup Register Bit Assignments
External Management Mode Initialization
The LXT914 Repeater operates in the External management mode when the LOC/EXT pin is tied
Low. In the External mode, the serial port is a bidirectional interface between the
LXT914 Repeater and an external management device (EMD). The serial port is used to download
initial setup parameters to the repeater and to monitor status reports from the repeater. The
LXT914 Repeater setup parameters can be changed at any time by the EMD. The initialization
process for each repeater in a managed mode configuration is the same, regardless of its position;
each repeater is connected directly to the EMD. Each LXT914 Repeater initializes as follows:
ERXJAB 1 = Enable Receive JAB (Long Packet) (Global)
DFIFOE
1. Syncs to the 10 MHz Serial Clock (SCLK) input. SCLK must be supplied from an external
2. Responds to SENI Low by enabling the SDI port.
3. Clocks 48 bits from the EMD into its setup register through the SDI port.
4. Once initialized, the LXT914 Repeater reports its status in a 48-bit serial stream after every
Register
DISAPx
DISTXx
DISRXx
DPFRM
DPRCx
ERSQx
DMJLP
DISLIx
DMCV
DSQE
SR(0)
SR(1)
SR(2)
SR(3)
SR(4)
SR(5)
RES
Bit
source.
packet transmission or interrupt event. Refer to
bit assignments and definitions.
1 = Disable Auto-Partitioning on Port x
1 = Disable Link Integrity on Port x (Twisted-pair ports only)
1 = Disable Polarity Reverse detection and Correction on Port x (Twisted-pair ports only)
1 = Disable Transmit on Port x
1 = Disable Receive on Port x
1 = Enable Reduced Squelch on Port x (Twisted-pair ports only)
1 = Disable entering Tx Collision state on reception of Manchester Code Violation
1 = Disable Signal Quality Error to provide heartbeat (AUI port only)
1 = Disable End-of-Frame checking for polarity correction (Global)
1 = Disable entering Tx Collision state on FIFO over/underflow condition (Global)
1 = Disable MJLP counter (Global)
Reserved. Must be set to 0.
DFIFOE
DISTX2
ERSQ1
DISLI3
RES
RES
D7
Intel
DISRX4
DISTX1
DPFRM
®
Order Number: 248989, Revision: 003
DISLI2
RES
RES
LXT914 Flexible Quad Ethernet Repeater
D6
DISTXA
DISRX3
DISLI1
DSQE
RES
RES
D5
DISAP4
DISRX2
DPRC4
DMCV
RES
RES
D4
Definition
Table 11
Intel
ERXJAB
DISAP3
DISRX1
DPRC3
RES
RES
®
D3
LXT914 Flexible Quad Ethernet Repeater
and
Table 12
DISRXA
DISAP2
DPRC2
ERSQ4
RES
RES
D2
for packet status register
DISAP1
DPRC1
DISTX4
ERSQ3
RES
RES
D1
31-Oct-2005
DISAPA
DISTX3
ERSQ2
DISLI4
RES
RES
D0
19