ISL36411DRZ-T7 Intersil, ISL36411DRZ-T7 Datasheet
ISL36411DRZ-T7
Specifications of ISL36411DRZ-T7
ISL36411DRZ-TS-TR
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QLX411RIQT7-TR
QLX411RIQT7-TR
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ISL36411DRZ-T7 Summary of contents
Page 1
... Twin-Axial Cable = 10m 28AWG 1.2V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. 1.2V Host Channel Adapter 10nF ...
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... PART NUMBER (Notes PART MARKING ISL36411DRZ-TS ISL36411DRZ ISL36411DRZ-T7 ISL36411DRZ NOTES: 1. “-TS” and “-T7” suffix is for Tape and Reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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Pin Functions and Definitions PIN NAME PIN NUMBER 13, 24, Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to DD 27, 28, 31, 32, ground is recommended for each of ...
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... Thermal Information Thermal Resistance (Typical QFN Package (Notes Operating Ambient Temperature Range 0°C to +85°C Storage Ambient Temperature Range . . . . . -55°C to +150°C Maximum Junction Temperature +125°C Pb-Free Reflow Profile see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CONDITION NRZ data applied to any channel ...
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Electrical Specifications V PARAMETERS SYMBOL Output Return Loss Limit (Differential) Output Return Loss Limit (Common Mode) Output Return Loss Limit (Com. to Diff. Conversion) Output Residual Jitter Output Transition Time t ...
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Typical Performance Characteristics Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched into the twin-ax cable using an SMA adapter card. The chip evaluation board is connected to the output ...
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IN[P] IN[N] Signal DT Detector FIGURE 3. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE ISL36411 Operation The ISL36411 is an advanced quad lane-extender for high-speed interconnects. A functional diagram of one of the four channels in the ISL36411 is ...
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ISL36411 CML Input and Output Buffers The input and output buffers for the high-speed data channels in the ISL36411 are implemented using CML (shown in Figures 4 and 5 IN[P] Ω 50O 50O Ω IN[N] FIGURE 4. CML ...
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Application Information Typical application schematic for ISL36411 is shown in Figure 6. 1.2V Bypass circuit for each V pin DD (*100pF capacitor should be positioned closest to the pin) NOTES: 15. See “Control Pin Boost Setting” on page 7 for ...
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... To address this, Intersil has developed its groundbreaking Q:ACTIVE® product line. By integrating its analog ICs inside cabling interconnects, Intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow’s datacenters. This new technology transforms passive cabling into intelligent “ ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries ...
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Package Outline Drawing L46.4x7 46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN) Rev 0, 9/09 4.00 6 PIN 1 INDEX AREA (4X) 0.05 TOP VIEW 0.70 ±0.05 SIDE VIEW ( 3. 2.50 5.50 ...