PI7C9X20505GPBNDE Pericom Semiconductor, PI7C9X20505GPBNDE Datasheet - Page 5

• Manufacturer Part Number: PI7C9X20505GPBNDE
• Description: IC PCIE PACKET SWITCH 256BGA
• Manufacturer: Pericom Semiconductor
• Series: GreenPacket™r

Specifications of PI7C9X20505GPBNDE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

TABLE OF CONTENTS
1
2
3
4
5
6
7
June 2009 – Revision 1.5
Pericom Semiconductor
3.1
3.2
3.3
3.4
3.5
3.6
4.1
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
6.1
6.2
7.1
7.2
FEATURES.........................................................................................................................................................10
GENERAL DESCRIPTION..............................................................................................................................11
PIN DESCRIPTION...........................................................................................................................................12
PIN ASSIGNMENTS .........................................................................................................................................16
FUNCTIONAL DESCRIPTION.......................................................................................................................18
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................24
REGISTER DESCRIPTION.............................................................................................................................33
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
6.1.1
6.1.2
6.1.3
6.1.4
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
PORT CONFIGURATION SIGNALS .......................................................................................................12
HOT PLUG SIGNALS ...............................................................................................................................13
MISCELLANEOUS SIGNALS..................................................................................................................13
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................14
POWER PINS.............................................................................................................................................15
PIN LIST
PHYSICAL LAYER CIRCUIT ..................................................................................................................18
DATA LINK LAYER (DLL)......................................................................................................................20
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................20
ROUTING ..................................................................................................................................................20
TC/VC MAPPING......................................................................................................................................21
QUEUE.......................................................................................................................................................21
TRANSACTION ORDERING...................................................................................................................22
PORT ARBITRATION ..............................................................................................................................23
VC ARBITRATION ...................................................................................................................................23
FLOW CONTROL .....................................................................................................................................23
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................23
EEPROM INTERFACE .............................................................................................................................24
SMB
REGISTER TYPES ....................................................................................................................................33
TRANSPARENT MODE CONFIGURATION REGISTERS ....................................................................33
PH .......................................................................................................................................................21
PD .......................................................................................................................................................21
NPHD .................................................................................................................................................21
CPLH ..................................................................................................................................................21
CPLD ..................................................................................................................................................22
AUTO MODE EERPOM ACCESS .....................................................................................................24
EEPROM MODE AT RESET..............................................................................................................24
EEPROM SPACE ADDRESS MAP ....................................................................................................24
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS..........................................26
VENDOR ID REGISTER – OFFSET 00h ...........................................................................................35
DEVICE ID REGISTER – OFFSET 00h.............................................................................................35
COMMAND REGISTER – OFFSET 04h............................................................................................35
PRIMARY STATUS REGISTER – OFFSET 04h.................................................................................36
REVISION ID REGISTER – OFFSET 08h .........................................................................................36
CLASS CODE REGISTER – OFFSET 08h .........................................................................................36
US
INTERFACE .................................................................................................................................32
OF
256-PIN PBGA ......................................................................................................................16
Page 5 of 81
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