PI7C8150ANDE Pericom Semiconductor, PI7C8150ANDE Datasheet - Page 107
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PI7C8150ANDE
Manufacturer Part Number
PI7C8150ANDE
Description
IC PCI-PCI BRIDGE 2PORT 256-PBGA
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8150ANDE.pdf
(111 pages)
Specifications of PI7C8150ANDE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
06-0057
17.3
AC SPECIFICATIONS
1. See Figure 17-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface
signals are synchronized to S_CLKOUT.
3. Point-to-point signals are P_REQ_L, S_REQ_L[7:0], P_GNT_L, S_GNT_L[7:0],
HSLED, HS_SW_L, HS_EN, and ENUM_L. Bused signals are P_AD, P_BDE_L, P_PAR,
P_PERR_L, P_SERR_L, P_FRAME_L, P_IRDY_L, P_TRDY_L, P_LOCK_L,
P_DEVSEL_L, P_STOP_L, P_IDSEL, S_AD, S_CBE_L, S_PAR, S_PERR_L,
S_SERR_L, S_FRAME_L, S_IRDY_L, S_TRDY_L, S_LOCK_L, S_DEVSEL_L, and
S_STOP_L.
4. REQ_L signals have a setup of 10 and GNT_L signals have a setup of 12.
Symbol
Tsu
Tsu(ptp)
Th
Tval
Tval(ptp)
Ton
Toff
Figure 17-1
Parameter
Input setup time to CLK – bused signals
Input setup time to CLK – point-to-point
Input signal hold time from CLK
CLK to signal valid delay – bused signals
CLK to signal valid delay – point-to-point
Float to active delay
Active to float delay
PCI Signal Timing Measurement Conditions
Page 107 of 111
1,2
1,2
1,2
1,2,3
1,2,3
1,2,3
1,2,3
Min.
3
5
0
2
2
2
-
2-PORT PCI-TO-PCI BRIDGE
66 MHz
APRIL 2006 – Revision 1.1
Max.
-
-
-
6
6
-
14
Min.
7
10, 12
0
2
2
2
-
33 MHz
4
PI7C8150A
Max.
-
-
-
11
12
-
28
Units
ns