PI7C8150ANDE Pericom Semiconductor, PI7C8150ANDE Datasheet - Page 52
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PI7C8150ANDE
Manufacturer Part Number
PI7C8150ANDE
Description
IC PCI-PCI BRIDGE 2PORT 256-PBGA
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8150ANDE.pdf
(111 pages)
Specifications of PI7C8150ANDE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
06-0057
6
6.1
PI7C8150A does not have a hardware mechanism to guarantee data synchronization for
posted write transactions. Therefore, all posted write transactions must be followed by a
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
ERROR HANDLING
PI7C8150A checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C8150A always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C8150A
always attempts to be transparent when reporting errors, but this is not always possible,
given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8150A implements the following:
This chapter provides detailed information about how PI7C8150A handles errors.
It also describes error status reporting and error operation disabling.
ADDRESS PARITY ERRORS
PI7C8150A checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C8150A detects an address parity error on the primary interface,
the following events occur:
When PI7C8150A detects an address parity error on the secondary interface, the following
events occur:
PERR_L and SERR_L signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR_L event disable register
If the parity error response bit is set in the command register, PI7C8150A does not
claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally
and accepts the transaction if it is directed to or across PI7C8150A.
PI7C8150A sets the detected parity error bit in the status register.
PI7C8150A asserts P_SERR_L and sets signaled system error bit in the status register,
if both the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the command register.
Page 52 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A