PI7C8150ANDE Pericom Semiconductor, PI7C8150ANDE Datasheet - Page 57

• Manufacturer Part Number: PI7C8150ANDE
• Description: IC PCI-PCI BRIDGE 2PORT 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ANDE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
6.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8150A responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
Similarly, during upstream posted write transactions, when PI7C8150A responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
PI7C8150A completes the transaction normally.
PI7C8150A asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C8150A sets the parity error detected bit in the status register of the primary
interface.
PI7C8150A captures and forwards the bad parity condition to the secondary bus.
PI7C8150A completes the transaction normally.
PI7C8150A asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C8150A sets the parity error detected bit in the status register of the secondary
interface.
PI7C8150A captures and forwards the bad parity condition to the primary bus.
PI7C8150A completes the transaction normally.
PI7C8150A sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
PI7C8150A asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
The SERR_L enable bit is set in the command register.
The posted write parity error bit of P_SERR_L event disable register is not
set.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C8150A has not detected the parity error on the primary (initiator) bus
which the parity error is not forwarded from the primary bus to the
secondary bus.
Page 57 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A