PI7C8150ANDE Pericom Semiconductor, PI7C8150ANDE Datasheet - Page 59
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PI7C8150ANDE
Manufacturer Part Number
PI7C8150ANDE
Description
IC PCI-PCI BRIDGE 2PORT 256-PBGA
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8150ANDE.pdf
(111 pages)
Specifications of PI7C8150ANDE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-PBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
06-0057
Table 6-2. Setting Secondary Interface Detected Parity Error Bit
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Table 6-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8150A detects a parity
error on the secondary interface.
Table 6-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
Table 6-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
X = don’t care
Secondary
Detected
Error Bit
0
1
0
0
0
0
0
1
0
0
0
1
X = don’t care
Primary
Parity Bit
0
0
1
0
0
0
1
0
0
0
1
0
X = don’t care
PI7C8150A must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Parity
Data
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Page 59 of 111
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Primary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Primary
Primary
Primary
Primary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
Was Detected
Was Detected
APRIL 2006 – Revision 1.1
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
PI7C8150A
Bits
Bits