PI7C8150ANDE Pericom Semiconductor, PI7C8150ANDE Datasheet - Page 7

• Manufacturer Part Number: PI7C8150ANDE
• Description: IC PCI-PCI BRIDGE 2PORT 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ANDE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
11
12
13
14
10.1
10.2
10.3
12.1
12.2
12.3
13.1
13.2
14.1
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1.17
14.1.18
14.1.19
14.1.20
14.1.21
OFFSET 28h ....................................................................................................................................... 84
14.1.22
OFFSET 2Ch....................................................................................................................................... 84
14.1.23
14.1.24
14.1.25
14.1.26
14.1.27
14.1.28
14.1.29
14.1.30
14.1.31
14.1.32
PCI POWER MANAGEMENT .......................................................................... 72
RESET ................................................................................................................... 73
SUPPORTED COMMANDS............................................................................... 74
CONFIGURATION REGISTERS...................................................................... 77
GPIO CONTROL REGISTERS............................................................................................... 70
SECONDARY CLOCK CONTROL........................................................................................ 70
LIVE INSERTION ................................................................................................................... 72
PRIMARY INTERFACE RESET ............................................................................................ 73
SECONDARY INTERFACE RESET...................................................................................... 74
CHIP RESET............................................................................................................................ 74
PRIMARY INTERFACE ......................................................................................................... 74
SECONDARY INTERFACE................................................................................................... 76
CONFIGURATION REGISTER ............................................................................................. 77
VENDOR ID REGISTER – OFFSET 00h......................................................................... 78
DEVICE ID REGISTER – OFFSET 00h .......................................................................... 78
COMMAND REGISTER – OFFSET 04h.......................................................................... 78
STATUS REGISTER – OFFSET 04h ................................................................................ 79
REVISION ID REGISTER – OFFSET 08h ...................................................................... 80
CLASS CODE REGISTER – OFFSET 08h....................................................................... 80
CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 80
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 80
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 81
PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 81
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 81
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 81
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 81
I/O BASE REGISTER – OFFSET 1Ch.......................................................................... 81
I/O LIMIT REGISTER – OFFSET 1Ch ........................................................................ 82
SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 82
MEMORY BASE REGISTER – OFFSET 20h .............................................................. 83
MEMORY LIMIT REGISTER – OFFSET 20h............................................................. 83
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ................................ 83
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ............................ 84
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 84
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 85
ECP POINTER REGISTER – OFFSET 34h................................................................. 85
INTERRUPT LINE REGISTER – OFFSET 3Ch ......................................................... 85
INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 85
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 85
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 87
ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 88
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 88
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h ............................... 89
Page 7 of 111
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A