PI7C8150ANDE Pericom Semiconductor, PI7C8150ANDE Datasheet - Page 86

• Manufacturer Part Number: PI7C8150ANDE
• Description: IC PCI-PCI BRIDGE 2PORT 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ANDE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

06-0057
Bit
18
19
20
21
22
23
24
Function
ISA enable
VGA enable
Reserved
Master Abort
Mode
Secondary
Interface Reset
Fast Back-to-
Back Enable
Primary Master
Timeout
Type
R/W
R/W
R/O
R/W
R/W
R/W
R/W
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Reserved. Returns 0 when read. Reset to 0
Description
Modifies the bridge’s response to ISA I/O addresses, applying only
to those addresses falling within the I/O base and limit address
registers and within the first 64KB or PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the
last 768 bytes in each 1KB block
Reset to 0
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses
from primary to secondary
1: forward VGA compatible memory and I/O addresses from primary
to secondary regardless of other settings
Reset to 0
Control’s bridge’s behavior responding to master aborts on
secondary interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible by the
assertion of P_SERR_L if enabled
Reset to 0
Controls the assertion of S_RESET_L signal pin on the secondary
interface
0: does not force the assertion of S_RESET_L pin
1: forces the assertion of S_RESET_L
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not allow fast back-to-back transactions
1: enables fast back-to-back transactions
Reset to 0
Set’s the maximum number of PCI clocks the bridge will wait for an
initiator on the primary to repeat a delayed transaction request. The
counter starts right after the delayed transaction is at the front of the
queue. If the master has not repeated at least once before the counter
expires, the bridge discards the transaction from the queue.
0: 2
1: 2
Reset to 0
15
10
PCI clocks
PCI clocks
2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 1.1
PI7C8150A