PI7C8150BNDE Pericom Semiconductor, PI7C8150BNDE Datasheet - Page 100
![IC PCI-PCI BRIDGE ASYNC 256-PBGA](/photos/6/93/69399/pi7c8150bnde_sml.jpg)
PI7C8150BNDE
Manufacturer Part Number
PI7C8150BNDE
Description
IC PCI-PCI BRIDGE ASYNC 256-PBGA
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8150BNDE.pdf
(109 pages)
Specifications of PI7C8150BNDE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
256-PBGA
Mounting Type
Surface Mount
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI7C8150BNDE
Manufacturer:
CYPRESS
Quantity:
101
Part Number:
PI7C8150BNDE
Manufacturer:
PERICOM
Quantity:
20 000
16.3
16.4
16.5
16.6
TAP TEST DATA REGISTERS
The PI7C8150B contains two test data registers (bypass and boundary-scan). Each test
data register selected by the TAP controller is connected serially between TDI and TDO.
TDI is connected to the test data register’s most significant bit. TDO is connected to the
least significant bit. Data is shifted one bit position within the register towards TDO on
each rising edge of TCK. While any register is selected, data is transferred from TDI to
TDO without inversion. The following sections describe each of the test data registers.
BYPASS REGISTER
The required bypass register, a one-bit shift register, provides the shortest path between
TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test
data to and from other components on the board. This path can be selected when no test
operation is being performed on the PI7C8150B.
The boundary-scan register contains a cell for each pin as well as control cells for I/O and
the high-impedance pin.
Table Table 16-1 shows the bit order of the PI7C8150B boundary-scan register. All table
cells that contain “Control” select the direction of bi-directional pins or high-impedance
output pins. When a “1” is loaded into the control cell, the associated pin(s) are high-
impedance or selected as output.
The boundary-scan register is a required set of serial-shiftable register cells, configured in
master/slave stages and connected between each of the PI7C8150B’s pins and on-chip
system logic. The VDD, GND, and JTAG pins are NOT in the boundary-scan chain.
The boundary-scan register cells are dedicated logic and do not have any system function.
Data may be loaded into the boundary-scan register master cells from
the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and
EXTEST instructions. Parallel loading takes place on the rising edge of TCK.
Data may be scanned into the boundary-scan register serially via the TDI serial input pin,
clocked by the rising edge of TCK. When the required data has been loaded into the
master-cell stages, it can be driven into the system logic at input pins or onto the output
pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan
register by means of the TDO serial output pin at the falling edge of TCK.
TAP CONTROLLER
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that
controls the sequence of test logic operations. The TAP can be controlled via a bus master.
The bus master can be either automatic test equipment or a component (i.e., PLD) that
interfaces to the TAP. The TAP controller changes state only in response to a rising edge of
BOUNDARY-SCAN REGISTER
Page 100 of 109
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B