PI7C8150BMAE Pericom Semiconductor, PI7C8150BMAE Datasheet - Page 6
![IC PCI-PCI BRIDGE ASYNC 208-FQFP](/photos/6/94/69401/pi7c8150bmae_sml.jpg)
PI7C8150BMAE
Manufacturer Part Number
PI7C8150BMAE
Description
IC PCI-PCI BRIDGE ASYNC 208-FQFP
Manufacturer
Pericom Semiconductor
Datasheet
1.PI7C8150BNDE.pdf
(109 pages)
Specifications of PI7C8150BMAE
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
208-FQFP
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Supply Current (max)
510 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C8150BMAE
Manufacturer:
PERICOM
Quantity:
20 000
5
6
7
8
9
10
11
12
4.3
4.4
5.1
5.2
5.3
5.4
6.1
6.2
6.3
6.4
7.1
7.2
7.3
8.1
8.2
9.1
9.2
9.3
10.1
10.2
10.3
12.1
12.2
12.3
4.3.1
4.3.2
4.4.1
4.4.2
TRANSACTION ORDERING.......................................................................................................... 46
ERROR HANDLING......................................................................................................................... 50
6.2.1
6.2.2
6.2.3
6.2.4
EXCLUSIVE ACCESS ...................................................................................................................... 61
7.2.1
7.2.2
PCI BUS ARBITRATION................................................................................................................. 64
8.2.1
8.2.2
8.2.3
8.2.4
CLOCKS ............................................................................................................................................. 67
GENERAL PURPOSE I/O INTERFACE.................................................................................... 68
PCI POWER MANAGEMENT .................................................................................................... 71
RESET............................................................................................................................................. 72
MEMORY ADDRESS DECODING ........................................................................................... 43
VGA SUPPORT........................................................................................................................... 45
TRANSACTIONS GOVERNED BY ORDERING RULES ....................................................... 47
GENERAL ORDERING GUIDELINES ..................................................................................... 47
ORDERING RULES.................................................................................................................... 48
DATA SYNCHRONIZATION .................................................................................................... 49
ADDRESS PARITY ERRORS .................................................................................................... 50
DATA PARITY ERRORS ........................................................................................................... 51
DATA PARITY ERROR REPORTING SUMMARY................................................................. 56
SYSTEM ERROR (SERR_L) REPORTING............................................................................... 60
CONCURRENT LOCKS ............................................................................................................. 61
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B .................................................... 61
ENDING EXCLUSIVE ACCESS................................................................................................ 63
PRIMARY PCI BUS ARBITRATION ........................................................................................ 64
SECONDARY PCI BUS ARBITRATION.................................................................................. 64
PRIMARY CLOCK INPUTS....................................................................................................... 67
SECONDARY CLOCK OUTPUTS ............................................................................................ 67
ASYNCHRONOUS MODE......................................................................................................... 67
GPIO CONTROL REGISTERS................................................................................................... 68
SECONDARY CLOCK CONTROL ........................................................................................... 69
LIVE INSERTION ....................................................................................................................... 70
PRIMARY INTERFACE RESET................................................................................................ 72
SECONDARY INTERFACE RESET.......................................................................................... 72
CHIP RESET................................................................................................................................ 73
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 44
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ................. 44
VGA MODE......................................................................................................................... 46
VGA SNOOP MODE........................................................................................................... 46
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE.......... 51
READ TRANSACTIONS .................................................................................................... 51
DELAYED WRITE TRANSACTIONS............................................................................... 52
POSTED WRITE TRANSACTIONS.................................................................................. 55
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ..................................... 61
LOCKED TRANSACTION IN UPSTREAM DIRECTION .............................................. 63
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER.................... 64
PREEMPTION .................................................................................................................... 66
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER...................... 66
BUS PARKING.................................................................................................................... 66
Page 6 of 109
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B