PI7C8154BNAE Pericom Semiconductor, PI7C8154BNAE Datasheet - Page 19

• Manufacturer Part Number: PI7C8154BNAE
• Description: IC PCI-PCI BRIDGE ASYNC 304-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 304-BGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.7
1.2.8
1.2.9
GENERAL PURPOSE I/O INTERFACE SIGNALS
JTAG BOUNDARY SCAN SIGNALS
POWER AND GROUND
CONFIG66
PMEENA#
EEDATA
EECLK
EE_EN#
NO CONNECT
Name
GPIO[3:0]
Name
TCK
TMS
TDO
TDI
TRST#
Name
VDD
R22
D11
A22
A23
AC22
B6, AA22
Pin #
K2, K3, L4, L1
Pin #
N20
P21
P22
P23
N23
Pin #
A2, B1, B20, B23, D5, D6,
D10, D14, D15, D18, E22,
H4, H20, J1, J3, J21, M4,
M20, N4, R1, R23, T1, T4,
T20, W3, Y6, Y10, Y14,
Y18, Y22, AB19, AB23,
AC2, AC3, AC8, AC12,
AC16
Page 19 of 112
Type
Type
Type
I/O
TS
O
O
P
I
I
I
-
I
I
I
I
66MHz Configuration: This pin indicates if the
bridge is capable of running at 66MHz operation.
Tie HIGH to set bit [21] of offset 04h of the status
register.
Power Management Enable Support: This pin
sets bits [31:27] offset DEh of the Power
Management Capabilities Register. When tied
LOW, bits [31:27] offset DEh are set to 11111 to
indicate that the secondary devices are capable of
asserting PME#. When this pin is tied HIGH, bits
[31:27] offset DEh are set to 00000 to indicate that
PI7C8154B does not support the PME# pin.
EEPROM Data: Serial data interface to the
EEPROM
EEPROM Clock: Clock signal to the EEPROM
interface used during the autoload and VPD
functions
EEPROM Enable: Set to LOW to enable
EEPROM interface
No Connect
Description
General Purpose I/O Data Pins: The 4 general-
purpose signals are programmable as either input-
only or bi-directional signals by writing the GPIO
output enable control register in the configuration
space.
Description
Test Clock. Used to clock state information and
data into and out of the bridge during boundary
scan.
Test Mode Select. Used to control the state of the
Test Access Port controller.
Test Data Output. Used as the serial output for the
test instructions and data from the test logic.
Test Data Input. Serial input for the JTAG
instructions and test data.
Test Reset. Active LOW signal to reset the Test
Access Port (TAP) controller into an initialized
state.
Description
Power: +3.3V Digital power.
ASYNCHRONOUS 2-PORT
JUNE 2008 REVISION 1.1
PCI-to-PCI BRIDGE
Advance Information
PI7C8154B