NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet
NS7520B-1-C36
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NS7520B-1-C36 Summary of contents
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NS7520 Data Sheet T he Digi NS7520 is a high-performance, highly integrated, 32-bit system-on-a chip ASIC designed for use in intelligent networked devices and Internet appliances. The NS7520 is based on the standard architecture in the NET+ARM™ family of devices. ...
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Contents NS7520 Overview........................................................................... 1 Key Features................................................................................ 2 Operating frequency ...................................................................... 3 Packaging and pinout ..................................................................... 4 Pinout detail tables ....................................................................... 6 System Bus interface............................................................. 6 Chip select controller........................................................... 10 Ethernet interface MAC......................................................... 11 “No connect” pins ............................................................... 13 General Purpose ...
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NS7520 Overview Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins. PLL System Clock BBUS 3.3V Serial-A Power 1.5V UART SPI 16 GPIO Serial transceivers and other devices Figure 1: NS7520 module overview Debugger JTAG ...
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Key Features This table lists the key features of the NS7520. CPU core ARM7TDMI 32-bit RISC processor 32-bit internal bus 32-bit ARM and 16-bit Thumb mode 15 general purpose ...
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Serial ports Two fully independent serial ports (UART, SPI) Digital phase lock loop (DPLL) for receive clock extractions 32-byte transmit/receive FIFOs Internal programmable bit-rate generators Bit rates 75–230400 in 16X mode Bit rates 1200 bps–4 Mbps in 1X mode Flexible ...
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Packaging and pinout Table 1 provides the NS7520 packaging dimensions. Figure 2 shows the NS7520 pinout and dimensions. Symbol Min Nom A ...
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Figure 2: NS7520 pinout and dimensions 177 PFBGA ...
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Pinout detail tables Each pinout table applies to a specific interface and contains the following information: Signal The pin name for each ...
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Symbol Pin ADDR20 N8 U ADDR19 P8 U ADDR18 M7 U ADDR17 R7 U ADDR16 N7 U ADDR15 R6 U ADDR14 M6 U ADDR13 P6 U ADDR12 N6 U ADDR11 M5 U ADDR10 P5 U ADDR9 N5 U ADDR8 R4 ...
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Symbol Pin DATA19 H3 DATA18 H4 DATA17 H1 DATA16 H2 DATA15 G4 DATA14 G1 DATA13 G3 DATA12 G2 DATA11 F4 DATA10 F2 ...
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Symbol Pin RW_ D6 BR_ D7 BG_ C7 BUSY_ B7 System bus interface signal descriptions Mnemonic Signal BCLK Bus clock ADDR[27:0] Address bus DATA[31:0] Data bus TS_ Transfer start BE_ Byte enable TA_ Transfer acknowledge TEA_ Transfer error acknowledge RW_ ...
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Chip select controller The NS7520 supports five unique chip select configurations. Symbol Pin CS4_ B4 CS3_ A4 CS2_ C5 CS1_ ...
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Ethernet interface MAC ENDEC values for general-purpose output and TXD refer to bits in the Ethernet General Note: Control register. ENDEC values for general-purpose input and RXD refer to bits in the Ethernet General Status register. In this table, GP ...
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Mnemonic Signal MDC MII management clock MDIO Management data IO TXCLK Transmit clock TXD3 Transmit data signals TXD2 TXD1 TXD0 ...
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Pin Description R13 Tie P12 Tie N12 XTALB1: Tie R15 XTALB2: NO CONNECT M11 NO CONNECT P11 NO CONNECT N11 NO CONNECT R12 NO CONNECT R14 NO CONNECT ...
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GPIO signal Serial Other signal signal PORTC5 RTSB_ REJECT_ 1 PORTC4 RXCB/RIB_/ RESET_ OUT1B_ 2 PORTC3 RXDB LIRQ3/ DACK2_ 2 PORTC2 DSRB_ LIRQ2/RPSF_ ...
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System clock and reset Symbol Pin XTALA1 K14 XTALA2 K12 PLLVDD (1.5V) L15 PLLVSS L12 RESET_ A10 Signal descriptions The NS7520 has three clock domains: System clock (SYSCLK) Bit rate generation and programmable timer reference clock (XTALA1/2) System bus clock ...
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System mode (test support) PLLTST_, BISTEN_, and SCANEN_ primary inputs control different test modes for both functional ...
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Mnemonic Signal TRST_ Test mode reset TCK Test mode clock Figure 3: TRST_ termination Power supply Signal Pin Oscillator VCC (3.3V) N13, C3 Core VCC (1.5V) R8, L14, C14, C13 I/O VCC (3.3V) E4, K4, M2, N3, P3, R5, H14, ...
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NS7520 modules CPU module The CPU uses an ARM7TDMI core processor. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, which result in high ...
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The NS7520 clock module creates the BCLK and FXTAL signals. Both signals are used internally, but BCLK can also be accessed at ball A6 by setting the BCLKD field in the System Control register to 0. BCLK functions as the ...
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The MAC module interfaces to an external physical layer (PHY) device using the MII standard defined by IEEE 802.3u. The MAC interface ...
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Serial controller The NS7520 supports two independent universal asynchronous/synchronous receiver/transmitter channels. Each channel supports these features: Independent programmable bit-rate generator UART and SPI (master) modes High-speed data transfer: x1 mode: 4Mbits/sec – x16 mode: 230 Kbits/sec – 32–byte TX FIFO ...
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NS7520 bootstrap initialization Many internal NS7520 features are configured when the ...
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DC characteristics and other operating specifications The NS7520 operates using an internal core V for the I/O cells, which drive/accept 3.3V levels. Table 4 provides the DC characteristics for inputs; Table 5 provides the DC characteristics for outputs. Sym Parameter ...
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Sym Parameter I Input current as “0” HighZ leakage current OZ C Pin capacitance IO Table ...
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Figure 6: Internal pulldown characteristics AC characteristics AC electrical specifications define the timing relationship between signals for interfaces and modes within a given interface. AC electrical specifications The AC electrical specifications are based on the system configuration shown in Figure ...
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SDRAM NS7520 Figure 7: System configuration for specified timing Signal BCLK A[27:0], CAS[3:0]_ CS[4:0]_ ...
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Signal CS[4:0]_, CAS[3:0], RW_, WE_, OE_ MDC, TXD[3:0], TXER, TXEN, TDO Table 8: Output buffer derating by load capacitance Oscillator Characteristics Figure 8 illustrates the recommended oscillator circuit details. Rise/fall time. The max rise/fall time on the system clock input ...
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Timing Diagrams Timing_Specifications All timing specifications consist of the relationship between a reference clock and a signal: There are bussed and non–bussed signals. Non–bussed signals separately ...
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Reset_timing From a cold start, RESET_ must be asserted until all power supplies are above their specified thresholds. An additional 8 microseconds is required for oscillator settling time (allow 40ms for crystal startup). Due to an internal three flip-flop delay ...
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SRAM timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer SRAM timing parameters Num Description 36 BCLK high ...
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SRAM read CS* controlled read (wait = 2) T1 BCLK TA* (Note-4) TEA* (Note-4) TA* (input) 6 A[27:0] 36 Note-2 BE[3:0]* 27 CS[4:0]* read D[31:0] 28 Sync OE* 18 CS0OE* 12 RW* Notes the next transfer is DMA, ...
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SRAM burst read CS* controlled, four word (4-2-2-2), burst read (wait = 2, BCYC = 01 BCLK TA* (Note-4) TEA*/LAST (Note-4) 6 A[27:0] 36 BE[3:0]* (Note-2) 27 CS[4:0]* ...
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SRAM burst read (2111) CS* controlled read (wait = 0, BCYC = 00 BCLK 30 TA* (Note-3) TEA* (Note-3) 6 A[27:0] 36 Note-2 BE[3:0]* 27 CS[4:0]* 10 read D[31:0] 28 Sync OE* 18 CS0OE* 12 RW* Notes: 1 ...
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SRAM write CS controlled write (internal and external), (wait = 2) T1 BCLK TA* (Note-4) TEA* (Note-4) TA* (input) 6 A[27:0] 36 Note-2 BE[3:0]* 27 CS[4:0]* 9 write D[31:0] 29 ...
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SRAM burst write CS controlled, four word (4-2-2-2), burst write (wait = 2, BCYC = 01 BCLK TA* (Note-4) TEA*/LAST (Note-4) 6 A[27:0] 36 BE[3:0]* (Note-2) 27 CS[4:0]* 9 write D[31:0] 29 Sync WE* 19 CS0WE* 12 ...
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SRAM OE read OE* controlled read (wait = 2) T1 BCLK TA* (Note-4) TEA*/LAST (Note-4) TA* (input) 6 A[27:0] 36 Note-2 BE[3:0]* CS[4:0]* read D[31:0] Async OE* CS0OE* 12 RW* ...
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SRAM OE burst read OE* controlled, four word (3-2-2-2), burst read (wait = 2, BCYC = 01 BCLK TA* (Note-4) TEA*/LAST (Note-4) 6 A[27:0] 36 BE[3:0]* (Note-2) 27 CS[4:0]* read D[31:0] Async OE* CS0OE* 12 RW* Notes: 1 ...
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SRAM WE write WE* controlled write (wait = 2) T1 BCLK TA* (Note-4) TEA*/LAST (note-4) TA* (input) 6 A[27:0] 36 Note-2 BE[3:0]* CS[4:0]* write D[31:0] Async WE* CS0WE* 12 RW* ...
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SRAM WE burst write WE* controlled, four word (3-2-2-2), burst write (wait = 2, BCYC = 01 BCLK TA* (Note-4) TEA*/LAST (Note-4) 6 A[27:0] 36 Note-2 BE[3:0]* 27 CS[4:0]* 9 write D[31:0] 29 Async WE* 19 CS0WE* 12 ...
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SDRAM timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer SDRAM timing parameters Num Description 36 BCLK ...
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SDRAM read SDRAM read, CAS latency = 2 T1 prechg active BCLK TA* (Note-5) TEA*/LAST* (Note-5) PortA2/AMUX 6 Non-muxed address 35 Muxed address 36 BE[3:0]* (DQM) read D[31:0] 27 CS[4:0]* 34 CAS3* (RAS) CAS2* (CAS CAS1* (WE) 34 ...
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SDRAM read SDRAM read, CAS latency = 1 T1 prechg BCLK TA* (Note-3) TEA*/LAST* (Note-3) PortA2/AMUX 6 Non-muxed address 35 Muxed address 36 BE[3:0]* (DQM) read D[31:0] 27 CS[4:0]* ...
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SDRAM burst read SDRAM read, CAS latency = 2 T1 prechg active BCLK TA* (Note-5) TEA*/LAST* (Note-5) PortA2/AMUX 6 Non-muxed address 35 Muxed address 36 BE*[3:0]* (DQM) read D[31:0] 27 CS[4:0]* 34 CAS3* (RAS) CAS2* (CAS CAS1* (WE) ...
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SDRAM burst read SDRAM read, CAS latency = 1 T1 prechg active BCLK TA* (Note-5) TEA*/LAST* (Note-5) PortA2/AMUX 6 Non-muxed address 35 Muxed address 36 BE[3:0]* (DQM) read D[31:0] ...
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SDRAM write SDRAM write T1 prechg BCLK TA* (Note-3) TEA*/LAST* (Note-3) PortA2/AMUX 6 Non-muxed address 35 Muxed address 36 Note-1 BE[3:0]* (DQM) write D[31:0] 27 CS[4:0]* 34 CAS3* (RAS) CAS2* (CAS) 34 CAS1* (WE) CAS0* (A10/AP) 12 RW* Notes: Port ...
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SDRAM burst write SDRAM burst write T1 prechg BCLK TA* (Note-3) TEA*/LAST* (Note-3) PortA2/AMUX 6 Non-muxed address 35 Muxed address 9 write D[31:0]1 36 BE[3:0]* (DQM) 27 CS[4:0]* 34 ...
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SDRAM load mode prechg BCLK 27 CS[4:0]* 34 CAS3* (RAS) CAS2* (CAS) 34 CAS1* (WE) CAS0* (A10/AP) A[13:0] SDRAM refresh prechg BCLK 27 CS[4:0]* 34 CAS3* (RAS) CAS2* (CAS) 34 CAS1* (WE) CAS0* (A10/AP) nop load ...
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DRAM timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer FP DRAM timing parameters Num ...
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FP DRAM read Fast Page read T1 BCLK TA* (Note-4) TEA*/LAST (Note-4) TA* (input) 36 Note-2 BE[3:0]* 6 Non-muxed address 35 Muxed address read D[31:0]1 OE* RAS[4:0]*1 Note-3 CAS[3:0]*1 PortA2/AMUX 12 RW* Notes the next transfer is DMA, ...
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DRAM burst read Fast Page burst read T1 TW BCLK TA* (Note-4) TEA*/LAST (Note-4) 36 Note-2 BE[3:0]* 6 Non-muxed address 35 Muxed address read D[31:0] 28 OE* ...
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FP DRAM write Fast Page write T1 BCLK TA* (Note-4) TEA*/LAST (Note-4) TA* (input) 36 Note-2 BE[3:0]* 6 Non-muxed address 35 Muxed address write D[31:0] WE* (FP)RAS[4:0]* Note-3 (FP)CAS[3:0]* PortA2/AMUX 12 RW* Notes the next transfer is DMA, ...
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DRAM burst write Fast Page burst write T1 TW BCLK TA* (Note-4) TEA*/LAST (Note-4) 36 Note-2 BE[3:0]* 6 Non-muxed address 35 Muxed address 9 writeD[31:0] 29 WE* ...
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Fast page refresh (RCYC = 00) RF1 RF2 RF3 BCLK 27 RAS[4:0 CAS3 CAS2 CAS1 CAS0* 12 WE* Fast page refresh (RCYC = 01) RF1 RF2 BCLK 27 RAS[4:0]* 43 CAS3* ...
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Fast page refresh (RCYC = 10) RF1 RF2 BCLK 27 RAS[4:0]* 43 CAS3* 43 CAS2* 43 CAS1* 43 CAS0* 12 WE* Fast page refresh (RCYC = 11) RF1 ...
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Ethernet timing Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer Ethernet timing parameters Num Description 44 TXCLK high to TXD*, TXEN, TXER valid 45 RXD*, RXER, RXDV, TXCOL, RXCRS valid to RXCLK high ...
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Ethernet cam timing RXCLK 50 RPSF_ REJECT_ ...
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JTAG timing Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer jtag arm ice timing parameters Num Description 54 TCK to TDO valid 55 TCK to TDO HighZ 56 TDI setup to TCK rising ...
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jtag bscan timing parameters Num Description 62 TCK to TDO valid 63 TCK to TDO HighZ 64 TDI setup to TCK rising 65 TDI hold from TCK rising 66 TRST* ...
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External DMA timing BCLK max frequency: 55.296 MHz Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer External DMA timing parameters Num Description 72 BCLK high to DACK* valid 75 BCLK high to DONE* ...
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Memory-to-memory external DMA T1 BCLK Mem signals (Note-2) R/W DREQ* 72 DACK* 75 DONE* (output) Notes null period sometimes occurs between ...
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Serial internal/external timing Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer SPI timing diagrams are in Chapter 10, "Serial Controller Module." See Figure 25, "SPI Note: master mode 0 and 1 two-byte transfer," ...
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synchronous serial internal clock SCLK Enable TXD RXD synchronous serial external ...
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GPIO timing Operating conditions: Temperature: -15.00 (min) Voltage: 1.60 (min) Output load: 25.0pf Input drive: CMOS buffer GPIO timing parameters Num Description 85 GPIO (setup) to BCLK rising 86 GPIO (hold) from BCLK rising 87 BCLK to GPIO (output) GPIO ...
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... Release date: March 2006 © Digi International Inc. 2005-2006 All rights reserved. Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a Digi International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of Digi International, Inc. in the United States and other countries worldwide. All other trademarks are the property of their respective owners ...