PEB2255H-V13 Infineon Technologies, PEB2255H-V13 Datasheet - Page 19

• Manufacturer Part Number: PEB2255H-V13
• Description: IC INTERFACE LINE 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB2255H-V13

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 80-SQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEB2255H-V13; PEB2255H-V13IN

Frame Aligner
• Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704 (E1) and for
• Programmable frame formats :
• Selectable conditions for recover/loss of frame alignment
• CRC4 to non-CRC4 interworking of ITU-T G. 706 Annex B (E1)
• Error checking via CRC4 procedures according to ITU-T G. 706 (E1)
• Error checking via CRC6 procedures according to ITU-T G. 706 and JT G.706 (T1/J1)
• Performs synchronization in ESF format according to NTT requirements (J1)
• Alarm and performance monitoring per second
• Insertion and extraction of alarm indication signals (AIS, Remote Yellow Alarm, AUXP)
• IDLE code insertion for selectable channels
• 8.192 MHz/2.048 MHz (E1) or 8.192 MHz/1.544 MHz (T1/J1) system clock frequency
• Selectable 2048/4096 kbit/s backplane interface with programmable receive/transmit
• Programmable tristate function of 4096 kbit/s output via RDO
• Elastic store for receive and transmit route clock wander and jitter compensation;
• Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass
• Supports fractional E1 or T1 access
• Flexible transparent modes
• Programmable In-Band Loop Code detection and generation (TR62411)
• Channel loop back, line loop back or payload loop back capabilities (TR54016)
• Pseudo random bit sequence (PRBS) generator and monitor
• Provides loop-timed mode
• Clear channel capabilities (T1/J1)
Signaling Controller
• HDLC controller
• DL-channel protocol for ESF format according to ANSI T1.403 or according to AT&T
• DL-channel protocol for F72 (SLC96) format
• CAS controller with last look capability, enhanced CAS- register access and freeze
• Robbed bit signaling capability (T1/J1)
Data Sheet
1544 kbit/s according to ITU-T G.704 and JT G.704 (T1/J1)
E1: Doubleframe, CRC Multiframe (E1)
T1: 4-Frame Multiframe (F4,FT), 12-Frame Multiframe (F12, D3/4), Extended
Superframe (F24, ESF), Remote Switch Mode (F72, SLC96)
16 bit counter for CRC-, framing errors, code violations, error monitoring via E bit and
SA6 bit (E1), errored blocks, PRBS bit errors
timeslot offset
controlled slip capability and slip indication
Bit stuffing, CRC check and generation, flag generation, flag and address recognition,
handling of bit oriented functions, programmable preamble
TR54016 (T1/J1)
signaling indication
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FALC-LH V1.3
Introduction
PEB 2255
2000-07