AD9888KS-140 Analog Devices Inc, AD9888KS-140 Datasheet
AD9888KS-140
Specifications of AD9888KS-140
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AD9888KS-140 Summary of contents
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FEATURES 205 MSPS Maximum Conversion Rate 500 MHz Programmable Analog Bandwidth 0 1.0 V Analog Input Range Less than 450 ps p-p PLL Clock Jitter @ 205 MSPS 3.3 V Power Supply Full Sync Processing Sync Detect for ...
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... IV 3.0 3.3 3.6 3.0 V 200 850 1050 –2– AD9888KS-170 AD9888KS-205 Typ Max Min Typ Max 8 8 ±0.6 +1.25/–1.0 ±0.8 +1.50/–1.0 +1.50/–1.0 +1.80/–1.0 ±0.75 ±2.25 ±1.0 ±3.75 ±2.75 ±4.25 Guaranteed Guaranteed 0.5 0.5 1.0 100 ...
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... JC Thermal Resistance —Junction-to-Ambient JA Thermal Resistance NOTES 1 AD9888KS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz. 2 See Figure 23. 3 VCO Range = 10, Charge Pump Current = 100, PLL Divider = 1693. 4 VCO Range = 11, Charge Pump Current = 100, PLL Divider = 2159. 5 DEMUX = 1, DATACK and DATACK Load = 15 pF, Data Load = 5 pF. ...
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AD9888 REF BYPASS 3 GND 4 GND AIN AIN 9 RMIDSCV GND 11 12 SOGIN0 AIN 14 V ...
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Pin Type Mnemonic Analog Video Inputs R 0 AIN G 0 AIN B 0 AIN R 1 AIN G 1 AIN B 1 AIN Sync/Clock Inputs HSYNC0 VSYNC0 SOGIN0 HSYNC1 VSYNC1 SOGIN1 CLAMP COAST CKEXT CKINV Sync Outputs HSOUT VSOUT ...
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AD9888 Mnemonic Description Inputs R 0 Channel 0 Analog Input for RED AIN G 0 Channel 0 Analog Input for GREEN AIN B 0 Channel 0 Analog Input for BLUE AIN R 1 Channel 1 Analog Input for RED AIN ...
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Mnemonic Description CKINV Sampling Clock Inversion (Optional) This pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180°. This is in support of Alternate Pixel Sampling mode, wherein higher frequency ...
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AD9888 Mnemonic Description FILT External Filter Connection For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node. Power ...
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Sync Processing The AD9888 contains circuitry that enables it to accept com- posite sync inputs, such as Sync-on-Green or the trilevel syncs found in digital TV signals. A complete description of the sync processing functionality is found in the Sync ...
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AD9888 The offset controls provide a ±63 LSB adjustment range. This range is connected with the full-scale range the input range is doubled (from 0 1.0 V), the offset step size is also doubled (from 2 ...
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0.0039 F 0.039 F R 3.3k FILT Figure 6. PLL Loop Filter Detail Four programmable registers are provided to optimize the performance of the PLL. These registers are: 1. The 12-Bit Divisor Registers. The input Hsync frequencies ...
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AD9888 4. The 5-Bit Phase Adjust Register. The phase of the generated sampling clock may be shifted to locate an optimum sampling point within a clock cycle. The Phase Adjust Register pro- vides 32 phase-shift steps of 11.25° each. The ...
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TIMING The following timing diagrams show the operation of the AD9888 analog interface in all clock modes. The part establishes timing by sending the sample that corresponds to the pixel digitized when the leading edge of Hsync occurs sent to ...
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AD9888 P0 P1 RGBIN HSYNC PXCK HS 8 PIPE DELAY ADCCK DATACK DOUTA HSOUT RGBIN HSYNC PXCK HS 8 PIPE DELAY ADCCK DATACK DOUTA HSOUT Figure 14. Single-Channel Mode, Two Pixels/Clock (Even ...
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P0 P1 RGBIN HSYNC PXCK HS 7 PIPE DELAY ADCCK DATACK DOUTA DOUTB HSOUT Figure 16. Dual-Channel Mode, Interleaved Outputs P0 P1 RGBIN HSYNC PXCK HS ADCCK DATACK DOUTA DOUTB HSOUT RGBIN ...
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AD9888 RGBIN HSYNC PXCK HS ADCCK DATACK DOUTA DOUTB HSOUT Figure 19. Dual-Channel Mode, Interleaved Outputs, Two Pixels/Clock (Odd Pixels RGBIN HSYNC PXCK HS ...
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P0 P1 RGBIN HSYNC PXCK HS 8 PIPE DELAY ADCCK DATACK GOUTA ROUTA HSOUT 2-WIRE SERIAL REGISTER MAP The AD9888 is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to ...
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AD9888 Read and Hex Write or Default Address Read Only Bits Value 0EH R/W 7:0 0******* Sync Control *1****** **0***** ***0**** ****0*** *****0** ******0* *******0 0FH R/W 7:1 0******* *1****** **0***** ***0**** ****1*** *****1** ******1* 10H R/W 7:3 01111*** Sync-on-Green ...
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Read and Hex Write or Default Address Read Only Bits Value 14H RO 7:0 15H R/W 7:0 1******* *1****** **0***** ***0**** ****0*** *****11* *******0 16H R/W 7:0 11111111 Test Register 17H R/W 7:3 00000000 Test Register 18H RO 7:0 19H ...
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AD9888 2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 00 7-0 Chip Revision An 8-bit register that represents the silicon revision. Revision 0 = 0000 0000, Revision 1 = 0000 0001. PLL DIVIDER CONTROL 01 7-0 PLL Divide Ratio MSBs The ...
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A value not supported. For the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the Hsync ...
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AD9888 Table XI. Active Hsync Override Settings Override Result 0 Auto determines the active interface. 1 Override, Bit 3, determines the active interface. The default for this register Active Hsync Select This bit is used under ...
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COAST Input Polarity A bit to indicate the polarity of the COAST signal that is applied to the PLL COAST input. Table XX. COAST Input Polarity Settings CSTPOL Function 0 Active Low 1 Active High Active LOW means ...
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AD9888 14 7 Hsync Detect This bit is used to indicate when activity is detected on the selected Hsync input pin. If HSYNC is held high or low, activity will not be detected. Table XXV. Hsync Detection Results Detect Function ...
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MODE CONTROL Channel Mode A bit that determines whether all pixels are presented to a single port (A), or alternating pixels are demultiplexed to Ports A and B. Table XXXIII. Channel Mode Settings DEMUX Function 0 All ...
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AD9888 2-WIRE SERIAL CONTROL PORT A 2-wire serial control interface is provided two AD9888 devices may be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises a clock (SCL) ...
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Sync Processing Table XLII. Control of the Sync Block Muxes via the Serial Register Mux Serial Bus Control Bit Number(s) Control Bit State 1 and 2 0EH: Bit 0FH: Bit 0EH: Bit ...
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AD9888 BIT 7 BIT 6 SDA SCL SYNC SLICER MUX5 NEGATIVE PEAK CLAMP SOGIN0 SOGIN1 HSYNC0 HSYNC1 MUX5 ACTIVITY DETECT COAST VSYNC0 VSYNC1 MUX5 ACTIVITY DETECT The AD9888 can digitize graphics signals over a very wide range of frequencies (10 ...
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This can be mitigated by regulating the analog supply least PV , from a different, cleaner, power D source (for example, from supply also recommended to use a single ground ...
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AD9888 COPLANARITY 0.10 MAX OUTLINE DIMENSIONS 128-Lead Metric Quad Flat Package [MQFP] (S-128A) Dimensions shown in millimeters 17.45 17.20 16.95 14.20 3.40 14.00 MAX 13.80 1.03 128 1 0.88 0.73 SEATING PLANE TOP VIEW (PINS DOWN 0.50 0.50 ...
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Revision History Location 3/03—Data Sheet changed from REV REV. B. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . ...
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