PDI1394L40BEUM ST-Ericsson Inc, PDI1394L40BEUM Datasheet
PDI1394L40BEUM
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PDI1394L40BE-T
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PDI1394L40BEUM Summary of contents
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - Philips ...
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SEE THE LAST 2 PAGES OF THIS DATASHEET FOR A LIST OF ERRATA RELATED TO THIS PART. PDI1394L40 1394 enhanced AV link layer controller Preliminary specification Supersedes data of 2000 May 15 hilips Semiconductors INTEGRATED CIRCUITS 2000 Dec 15 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 1.0 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C 13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030 13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 13.2.7 Isochronous ...
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Philips Semiconductors 1394 enhanced AV link layer controller 1.0 FEATURES IEEE1394a and IEEE1394–1995 Standard Link Layer Controller Hardware Support for the IEC61883 International Standard of Digital Interface for Consumer Electronics Interface to any IEEE 1394–1995 or 1394a Physical Layer Interface ...
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Philips Semiconductors 1394 enhanced AV link layer controller 5.0 PIN CONFIGURATION Pin Function 1 HIF D15 2 HIF D14 3 HIF D13 4 HIF D12 5 GND HIF D11 8 HIF D10 9 HIF D9 10 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 6.0 FUNCTIONAL DIAGRAM HIF A[7:0] HIF D[15:8] HIF AD[7:0] HIF A8 HIF WRN HIF RDN HIF CSN HIF 16BIT HIF MUX RESETN HIF ALE HIF WAIT HIF INTN PD CYCLEIN CYCLEOUT CLK50 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 8.0 APPLICATION DIAGRAM MPEG OR DVC INTERFACE DECODER MPEG OR DVC INTERFACE DECODER DATA 16/ ADDRESS 9/ INTERRUPT & CONTROL HOST CONTROLLER 9.0 PIN DESCRIPTION 9.1 Host Interface PIN No. PIN SYMBOL ...
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Philips Semiconductors 1394 enhanced AV link layer controller 9.2 AV Interface 1 NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register (0x018)—default is transmit. PIN No. PIN SYMBOL ...
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Philips Semiconductors 1394 enhanced AV link layer controller 9.3 AV Interface 2 NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register—default is receive. PIN No. PIN SYMBOL I/O ...
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Philips Semiconductors 1394 enhanced AV link layer controller 9.4 Phy Interface PIN No. PIN SYMBOL I/O Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface of 82, 81, 80, 79, the IEEE 1394–1995 standard, Annex ...
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Philips Semiconductors 1394 enhanced AV link layer controller 10.0 RECOMMENDED OPERATING CONDITIONS SYMBOL SYMBOL PARAMETER PARAMETER V DC supply voltage CC V Input voltage I V High-level input voltage IH V Low-level input voltage IL I High-level output current OH ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.0 FUNCTIONAL DESCRIPTION 12.1 Overview The PDI1394L40 is an IEEE1394–1995 and IEEE1394.a compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG–2 and DVC codecs. The ...
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Philips Semiconductors 1394 enhanced AV link layer controller Port Dir AVxREADY Transmit Out The L40 is prepared to receive a byte. The attached device will not assert AVVALID for any cycle in which AVxRDY is false. Receive In The attached ...
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Philips Semiconductors 1394 enhanced AV link layer controller DEFAULT BUFFER SIZE Asynchronous Receive Response FIFO Asynchronous Receive Request FIFO Asynchronous Transmit Response FIFO Asynchronous Transmit Request FIFO Isochronous (AV) Transmit Buffer Isochronous (AV) Receive Buffer 12.3 Bushold and Link/PHY single ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.3.2 Single capacitor isolation The circuit example (Figure 3) shows the connections required to implement basic single capacitor Link/PHY isolation. NOTE: The isolation enablement pins on both devices are in their “1” ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.5 The host interface The host interface allows an 8 bit or 16 bit CPU to access all registers and the asynchronous packet queues designed to be easy to use ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.5.2 Write accesses To write to an internal register the host interface must collect the 4 byte values (8 bit mode word values (16 bit mode) into a 32 bit ...
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Philips Semiconductors 1394 enhanced AV link layer controller are continuous recommend that before the interrupt is acknowledged, the corresponding enable bit should be set to “0”, else the interrupt will immediately happen again.] SWPD is a control bit. ...
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Philips Semiconductors 1394 enhanced AV link layer controller In Little Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 3. .0 from the left (most significant) to right (least significant) as shown in Figure 5. To ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.5.6 The CPU bus interface signals The CPU interface is directly compatible with a wide range of microcontrollers, and supports both multiplexed and non-multiplex access. It uses separate HIF RDN, HIF WRN, ...
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Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIFA7–A0 HIFD15–D8 HIFAD7–AD0 A8 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 15 Figure 7. 16 Bit Write Cycle Non-multiplexed 18 Preliminary ...
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Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE AD7–AD0 A7–A0 HIFD15–D8 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. Second write cycle elongated by WAIT signal. 2000 Dec 15 t ALEH t ...
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Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE HIF AD7–AD0 HIF A7–A0 HIFD15–D8 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 15 t ALEH t PWALE ADDR DA TA ADDR LATCHED DATA ...
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Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE AD7–AD0 A7–A0 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 15 t ALEH t PWALE ADDR DATA ADDR LATCHED Figure 10. 8 Bit Write ...
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Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N t ALES HIF ALE HIF AD7–AD0 HIF A7–A0 A8 HIF RD_N HIF WR_N HIF_WAIT HIF_MUX HIF16BIT 2000 Dec 15 t ALEH t PWALE ADDR DA TA ADDR LATCHED Figure 11. ...
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Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIFA7–A0 HIFAD7–AD0 A8 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 15 Figure 12. 8 Bit Write Cycle Non-multiplexed 23 Preliminary specification ...
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Philips Semiconductors 1394 enhanced AV link layer controller HIF CS_N HIF RD_N HIF WR_N HIF A8 HIFA7–A0 HIFAD7–AD0 HIF_WAIT HIF_MUX HIF16BIT NOTE: 1. ALE line is held LOW. 2000 Dec 15 Figure 13. 8 Bit Read Cycle Non-multiplexed 24 Preliminary ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6 The Asynchronous Packet Interface The PDI1394L40 provides an interface to asynchronous data packets through the registers in the host interface. The format of the asynchronous packets is specified in the following ...
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Philips Semiconductors 1394 enhanced AV link layer controller Table 1. Asynchronous Transmit Fields Field Name spd This field indicates the speed at which this packet sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs undefined tLabel ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.2 No-data Transmit The no-data transmit formats are shown in Figures 14 and 15. The first quadlet contains packet control information. The second and third quadlets contain 16-bit destination ID and either ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.3 Quadlet Transmit Three quadlet transmit formats are shown below. In these figures: The first quadlet contains packet control information. The second and third quadlets contain 16-bit destination ID and either the ...
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Philips Semiconductors 1394 enhanced AV link layer controller ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.4 Block Transmit The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information. The second and third quadlets contain ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.5 Unformatted Transmit The unformatted transmit format is shown in Figure 21. The first quadlet contains packet control information. The remaining quadlets contain data that is transmitted without any formatting on the ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.7 Asynchronous Receive Packet Formats This section describes the asynchronous receive packet formats. Four basic asynchronous data packet formats and one confirmation format exist: Table 2. Asynchronous Data Packet Formats ITEM FORMAT ...
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Philips Semiconductors 1394 enhanced AV link layer controller Table 4. Acknowledge codes Code Name 0001 ack_complete The node has successfully accepted the packet. If the packet was a request subaction, the destination node has successfully completed the transaction and no ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.8 No-data Receive The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlet contain 16-bit ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.9 Quadlet Receive The quadlet receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit ...
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Philips Semiconductors 1394 enhanced AV link layer controller ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.10 Block receive The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.11 Asynchronous Stream Receive The Asynchronous streaming receive packet format is shown below. The first quadlet contains dataLength, tag, and Channel number for source identification, and synchronization information. The following quadlets contain ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.6.2.13 Link data confirmation formats After a request, response, or asynchronous stream packet is transmitted, the asynchronous transmitter assembles a Link data confirmation (see Figure 32) which is used to confirm the ...
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Philips Semiconductors 1394 enhanced AV link layer controller 12.7.1.1 Interrupt Hierarchy HIF INT_N GLOBCSR (0x018) NOTE read of the RDI register (0xB0) should be done before looking for an interrupt in the GLOBCSR register. ...
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Philips Semiconductors 1394 enhanced AV link layer controller REGISTER 31 ADDRESS IDREG BUS ID 0x000 LNKCTL BSYCTRL 0x004 LNKPHYINTACK 0x008 LNKPHYINTE 0x00C CYCTM CYCLE_SECONDS 0x010 PHYACS PHYRGAD 0x014 0 0 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 31 REGISTER ADDRESS ITXCTL 0x034 ITXMEM 0x038 <RESERVED> 0x03C IRXPKCTL 0x040 0 0 IRXHQ1 SID 0x044 IRXHQ2 FMT 0x048 IRXINTACK 0x04C IRXINTE 0x050 IRXCTL 0x054 IRXMEM 0x058 <RESERVED> 0x05C . . . ...
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Philips Semiconductors 1394 enhanced AV link layer controller 31 REGISTER ADDRESS ASYCTL 0x080 ASYMEM 0x084 TX_RQ_NEXT 0x088 TX_RQ_LAST 0x08C TX_RP_NEXT 0x090 TX_RP_LAST 0x094 RREQ 0x098 RRSP 0x09C ASYINTACK 0x0A0 ASYINTE 0x0A4 <RESERVED> 0x0A8 0x0AC RDI 0x0B0 0 0 2000 Dec ...
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Philips Semiconductors 1394 enhanced AV link layer controller REGISTER 31 ADDRESS <RESERVED> 0x0B4 . . . . 0x0F0 SHADOW_REG byte 0 0x0F4 INDADDR 0x0F8 INDDATA 0x0FC 2000 Dec byte 1 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.1 Link Control Registers ID Register (IDREG) – Base Address: 0x000 13.1.1 The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus ...
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Philips Semiconductors 1394 enhanced AV link layer controller Bit 22: R Little Endian (LTLEND): Refers to the state of the endianess of the data and address lines connected to the ’L40. This bit reflects the state of the AV2ERR0/LTLEND pin ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008 The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to generate ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’ ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014 This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register. When ...
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Philips Semiconductors 1394 enhanced AV link layer controller Bit 16: R/W Direction of AVPORT1 (DIRAV1): A ‘1’ enables AVPORT1 as a transmitter, thus AVPORT1 pins are inputs. A ‘0’ configures AVPORT1 as a receiver, AVPORT1 pins are outputs in this ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2 AV (Isochronous) Transmitter and Receiver Registers 13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020 This register allows the user to set up the appropriate AV packets from ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024 The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter. Bits 2, 3, and 4 “auto ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040 NOTE: When receiver reset is required, first disable receiver (EN_IRX = 0), then wait until Rx FIFO is emptied, then perform the ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044 This quadlet represents the last received header value when AV receiver is operating ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.3 Asynchronous Control and Status Interface 13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098 3130 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4 Reset Value 0x00000000 Bits16..0 are interrupt enable bits for the Asynchronous RX/TX Interrupt ...
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Philips Semiconductors 1394 enhanced AV link layer controller Bit 3: R/W PLI: PHY – link interface initialized interrupt. This interrupt indicates when the PHY – link initialization routine has been accomplished. This bit will be set upon completion of the ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.4 Indirect Address Registers 13.4.1 The host interface register set has been extended to provide additional control and data registers for FIFO size control and copy protection control registers. These extensions have ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.5 Indirect Address Registers The following registers are defined in the indirect address space. Access to these registers must be made through the Indirect Address (INDADDR) and Indirect Data (INDDATA) registers. 13.5.1 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.5.1.2 Asynchronous Receive Request FIFO Size (RREQSIZE) – Indirect Address: 0x104 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 13.5.1.5 Isochronous Receiver FIFO Size (IRXSIZE) – Indirect Address: 0x120 ...
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Philips Semiconductors 1394 enhanced AV link layer controller 14.0 DC ELECTRICAL CHARACTERISTICS Table 9. DC Electrical Characteristics SYMBOL PARAMETER V LOW input voltage IL V HIGH input voltage Input threshold, rising edge IT1 V – Input threshold, ...
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Philips Semiconductors 1394 enhanced AV link layer controller 15.0 AC CHARACTERISTICS GND = SYMBOL PARAMETER t PERIOD (parallel AV clock period mode clock setup time clock input hold ...
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Philips Semiconductors 1394 enhanced AV link layer controller 16.0 TIMING DIAGRAMS 16.1 AV Interface Operation AVCLK MESSAGE AV D[7:0] AVSYNC AVVALID AVERR[0] ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR AVERR[1] Figure 35. AV Parallel Interface Operation Diagram ...
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Philips Semiconductors 1394 enhanced AV link layer controller 16.3 PHY-Link Interface Critical Timings SCLK PHY D[0:7], PHY CTL[0:1] Figure 38. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms PHY D[0:7], PHY CTL[0:1], LREQ Figure 39. PHY D[0:7], PHY ...
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Philips Semiconductors 1394 enhanced AV link layer controller 16.4 Host Interface Critical Timings READ HIF A[7:0] HIF CS_N HIF RD_N HIF D[7: WAIT WAIT WRITE HIF WR_N HIF D[7: ...
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Philips Semiconductors 1394 enhanced AV link layer controller SCLK CYCLEIN CYCLEOUT 16.6 RESET Timings RESET_N 2000 Dec 15 50 50% Figure 42. CYCLEOUT Waveforms 50% 50% t RESET SV00698 Figure 43. RESET_N Waveform 73 Preliminary specification PDI1394L40 50% ...
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Philips Semiconductors 1394 enhanced AV link layer controller LQFP144: plastic low profile quad flat package; 144 leads; body 1.4 mm 2000 Dec 15 74 Preliminary specification PDI1394L40 SOT486-1 ...
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Philips Semiconductors 1394 enhanced AV link layer controller Data sheet status Data sheet Product Definition status status Objective Development This data sheet contains the design target or goal specifications for product development. specification Specification may change in any manner without ...
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PDI1394L40 1394 ENHANCED AV LINK LAYER CONTROLLER (This errata list refers only to version 0301 of the L40 chip... package date codes after 0030 and the L40 Data Sheet dated 2000 December 15) Chip Errata: E–1 AV1READY pin initialization state ...
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E–4 When L40 is used with IEEE 1394–1995 compatible PHYs, RDI register bit ”PLI” does not function. Description of expected operation: When the L40 is placed in power–down mode (either by setting the SWPD bit in the RDI register or ...