HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 126
HD64570F16
Manufacturer Part Number
HD64570F16
Description
IC SCA SRL COMM ADAPTER 88QFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64570F16.pdf
(469 pages)
Specifications of HD64570F16
Applications
ISDN
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
88-QFP
Mounting Type
Surface Mount
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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HD64570F16V
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Bit 3: Reserved. This bit always reads 0 and must be set to 0.
Bit 2 (CRCCC: CRC Code Calculation): Specifies CRC code generation/detection in byte
synchronous or bit synchronous mode.
The polarity of the CRC code on the transmit and receive data lines depends on the protocol mode
as follows:
Byte synchronous: The calculated CRC value is transmitted on the TXDM line without
complementation, regardless of the setting of bits CRC1 and CRC0.
In received CRC calculations, the CRC value on the RXCM line is regarded as non-
complemented.
Bit synchronous: The one's complement of the calculated CRC value is transmitted on the TXDM
line, regardless of the setting of bits CRC1 and CRC0. In received CRC calculations, the CRC
value on the RXDM line is regarded as a one's complement.
Bits 1 0 (STOP1 STOP0/CRC1 CRC0: Stop Bit Length/CRC Calculation Expression and
Initial Value): Specify the stop bit length in asynchronous mode and the CRC calculation
expression in bit or byte synchronous mode.
Rev. 0, 07/98, page 110 of 453
Asynchronous mode
Reserved. This bit always reads 0 and must be set to 0.
Byte synchronous/Bit synchronous mode
CRCCC = 0: Disables CRC code generation/detection.
CRCCC = 1: Enables CRC calculation for transmission and reception in byte or bit
synchronous mode. Results of the CRC calculation for transmission are sent as CRC codes,
while results of the CRC calculation for reception are reflected by the CRCE bit of status
register 2 (ST2).
Deletes FCS (CRC) without transferring it to the receive buffer in bit synchronous mode.
Asynchronous mode
STOP1, STOP0 = 0, 0: Stop bit length = 1
STOP1, STOP0 = 0, 1: Stop bit length = 1.5
STOP1, STOP0 = 1, 0: Stop bit length = 2
STOP1, STOP0 = 1, 1: Reserved
Byte synchronous/Bit synchronous mode
CRC1 = 0:
and receiver
CRC1 = 1:
transmitter and receiver
CRC0 = 0:
Specifies CRC-16 (X16 + X15 + X2 + 1) for CRC calculators in the transmitter
Specifies CRC-CCITT (X16 + X12 + X5 + 1) for CRC calculators in the
Specifies all 0s as the CRC calculator initial value
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