NX3L2G66GT,115 NXP Semiconductors, NX3L2G66GT,115 Datasheet
NX3L2G66GT,115
Specifications of NX3L2G66GT,115
935284558115
NX3L2G66GT-G
NX3L2G66GT-G
Available stocks
Related parts for NX3L2G66GT,115
NX3L2G66GT,115 Summary of contents
Page 1
NX3L2G66 Dual low-ohmic single-pole single-throw analog switch Rev. 5 — 7 January 2011 1. General description The NX3L2G66 is a dual low-ohmic single-pole single-throw analog switch. Each switch has two input/output terminals (nY and nZ) and an active HIGH enable ...
Page 2
... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C NX3L2G66GT −40 °C to +125 °C NX3L2G66GD −40 °C to +125 °C NX3L2G66GM 5. Marking [1] Table 2. Marking codes Type number NX3L2G66GT NX3L2G66GD NX3L2G66GM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. ...
Page 3
... NXP Semiconductors 7. Pinning information 7.1 Pinning NX3L2G66 GND 4 Transparent top view Fig 3. Pin configuration SOT833-1 (XSON8) Fig 5. Pin configuration SOT902-1 (XQFN8U) NX3L2G66 Product data sheet Dual low-ohmic single-pole single-throw analog switch 001aah373 Fig 4. NX3L2G66 terminal 1 index area Transparent top view All information provided in this document is subject to legal disclaimers. ...
Page 4
... NXP Semiconductors 7.2 Pin description Table 3. Pin description Symbol Pin SOT833-1 and SOT996 GND 4 1E Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
Page 5
... NXP Semiconductors 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb Δt/ΔV input transition rise and fall rate [1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0 ...
Page 6
... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions C input I capacitance C OFF-state S(OFF) capacitance C ON-state S(ON) capacitance 11.1 Test circuits GND V I − Fig 6. Test circuit for measuring OFF-state leakage current 11.2 ON resistance Table 8 ...
Page 7
... NXP Semiconductors Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Symbol Parameter ΔR ON resistance mismatch ON between channels R ON resistance (flatness) V ON(flat) [1] Typical values are measured at T [2] Measured at identical V , temperature and input voltage. CC [3] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical V temperature ...
Page 8
... NXP Semiconductors 11.3 ON resistance test circuit and graphs GND Fig 8. Test circuit for measuring ON resistance NX3L2G66 Product data sheet Dual low-ohmic single-pole single-throw analog switch R ON (Ω 001aaj223 (1) V (2) V (3) V (4) V (5) V (6) V Fig 9. All information provided in this document is subject to legal disclaimers. ...
Page 9
... NXP Semiconductors 1 (Ω) 1.2 0.8 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 10. ON resistance as a function of input voltage 1 1 (Ω) 0.8 0.6 0.4 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = − ...
Page 10
... NXP Semiconductors 1 (Ω) 0.8 0.6 0.4 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 14. ON resistance as a function of input voltage 3 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see ...
Page 11
... NXP Semiconductors 12.1 Waveform and test circuits nE input nY output OFF to HIGH HIGH to OFF Measurement points are given in Logic level the typical output voltage level that occurs with the output load. OH Fig 16. Enable and disable times Table 10. Measurement points Supply voltage ...
Page 12
... NXP Semiconductors 12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); V ≤ specified 2.5 ns Symbol Parameter THD total harmonic distortion −3 dB frequency f (−3dB) response α isolation (OFF-state) iso V crosstalk voltage ct Xtalk crosstalk Q charge injection ...
Page 13
... NXP Semiconductors Adjust f voltage to obtain 0 dBm level at output. Increase f i Fig 19. Test circuit for measuring the frequency response when channel is in ON-state Adjust f voltage to obtain 0 dBm level at input. i Fig 20. Test circuit for measuring isolation (OFF-state) NX3L2G66 Product data sheet Dual low-ohmic single-pole single-throw analog switch V 0 ...
Page 14
... NXP Semiconductors a. Test circuit b. Input and output pulse definitions Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch 20 log ( log Fig 22. Test circuit for measuring crosstalk between switches NX3L2G66 Product data sheet Dual low-ohmic single-pole single-throw analog switch ...
Page 15
... NXP Semiconductors a. Test circuit b. Input and output pulse definitions = ΔV × C Definition: Q inj O L ΔV = output voltage variation generator resistance. gen V = generator voltage. gen Fig 23. Test circuit for measuring charge injection NX3L2G66 Product data sheet Dual low-ohmic single-pole single-throw analog switch ...
Page 16
... NXP Semiconductors 13. Package outline XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
Page 17
... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 25. Package outline SOT996-2 (XSON8U) ...
Page 18
... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...
Page 19
... NXP Semiconductors 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 14. Revision history Document ID Release date NX3L2G66 v.5 20110107 • Modifications: Section NX3L2G66 v ...
Page 20
... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
Page 21
... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: NX3L2G66 Product data sheet Dual low-ohmic single-pole single-throw analog switch 16 ...
Page 22
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 4 9 Limiting values Recommended operating conditions Static characteristics 11.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 ...