DC1261A Linear Technology, DC1261A Datasheet - Page 6
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DC1261A
Manufacturer Part Number
DC1261A
Description
BOARD DEMO LTM8022
Manufacturer
Linear Technology
Series
µModuler
Specifications of DC1261A
Design Resources
LTM8022 Spice Model LTM8022 Gerber Files DC1261 Design File DC1261 Schematic
Main Purpose
DC/DC, Step Down
Outputs And Type
1, Non-Isolated
Power - Output
-
Voltage - Output
3.3V
Current - Output
1A
Voltage - Input
4.5 ~ 36 V
Regulator Topology
Buck
Frequency - Switching
600kHz
Board Type
Fully Populated
Utilized Ic / Part
LTM8022
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIN FUNCTIONS
LTM8022
V
internal regulator and to the internal power switch. This
pin must be locally bypassed with an external, low ESR
capacitor of at least 2.2μF.
V
capacitor and the output load between these pins and
GND pins.
AUX (Pin F5): Low current voltage source for BIAS. In
many designs, the BIAS pin is simply connected to V
The AUX pin is internally connected to V
adjacent to the BIAS pin to ease printed circuit board
routing. Although this pin is internally connected to V
do NOT connect this pin to the load. If this pin is not tied
to BIAS, leave it fl oating. The Application Information
section gives specifi c information about the BIAS and
AUX connections
BIAS (Pin G5): The BIAS pin connects to the internal power
bus. Connect to a power source greater than 2.4V. If the
output is greater than 2.4V, connect this pin there. If the
output voltage is less, connect this to a voltage source
between 2.4V and 16V. Also, make sure that BIAS + V
is less than 56V.
RUN/SS (Pin H5): Tie RUN/SS pin to ground to shut down
the LTM8022. Tie to 2.5V or more for normal operation.
If the shutdown feature is not used, tie this pin to the V
pin. RUN/SS also provides a soft-start function; see the
Applications Information section.
GND (Bank 3): Tie these GND pins to a local ground plane
below the LTM8022 and the circuit components. Return
the feedback divider (R
6
IN
OUT
(Bank 1): The V
(Bank 2): Power Output Pins. Apply the output fi lter
IN
pin supplies current to the LTM8022’s
ADJ
) to this pin.
OUT
and is placed
OUT
OUT
IN
IN
.
,
R
frequency of the LTM8022 by connecting a resistor from
this pin to ground. The Applications Information section of
the data sheet includes a table to determine the resistance
value based on the desired switching frequency. Minimize
capacitance at this pin.
SHARE (Pin F7): Tie this to the SHARE pin of another
LTM8022 when paralleling the outputs. Otherwise, leave
this pin fl oating.
SYNC (Pin G6): External Clock Synchronization Input.
Ground this pin for low ripple Burst Mode
low output loads, or connect to a stable voltage source
above 0.7V to disable Burst Mode operation. Do not leave
this pin fl oating. Tie to a clock source for synchronization.
Clock edges should have rise and fall times faster than
1μs. See Synchronization in the Applications Information
section.
PG (Pin H6): Open Collector Output of an Internal
Comparator. PG remains low until the ADJ pin is within
10% of the fi nal regulation voltage. PG output is valid when
V
not used, leave this pin fl oating.
ADJ (Pin H7): The LTM8022 regulates its ADJ pin to 0.79V.
Connect the adjust resistor from this pin to ground. The
value of R
(V
T
IN
OUT
(Pin G7): The R
is above 3.6V and RUN/SS is high. If this function is
– 0.79), where R
ADJ
is given by the equation, R
T
pin is used to program the switching
ADJ
is in kΩ.
ADJ
®
operation at
= 394.21/
8022fd