KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet
KIT_TC1797_SK
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KIT_TC1797_SK Summary of contents
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TC1797 32-Bit Single-Chip Microcontroller Data Sheet V1.1 2009- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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TC1797 32-Bit Single-Chip Microcontroller Data Sheet V1.1 2009- ...
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... Footnote 2 is added for EBU Burst Mode Access Timing section. Trademarks TriCore® trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MultiCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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BFCLKO Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5.3.8 JTAG Interface ...
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Summary of Features • High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) 1) – 180 or 150 MHz ...
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Two High-Speed Micro Link interface (MLI) for serial inter-processor communication – One MultiCAN Module with 4 CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer TM – One ...
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Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set, the temperature range, and the supply voltage • The package and the ...
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Introduction This Data Sheet describes the Infineon TC1797, a 32-bit microcontroller DSP, based on the Infineon TriCore Architecture. 2.1 About this Document This document is designed to be read primarily by design engineers and software engineers who need a ...
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In chapters describing the kernels ...
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Reserved, Undefined, and Unimplemented Terminology In tables where register bit fields are defined, the following conventions are used to indicate undefined and unimplemented function. Furthermore, types of bits and bit fields are defined using the abbreviations as shown in ...
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Table 3 Access Terms Symbol Description U Access Mode: Access permitted in User Mode Reset Value: Value or bit is not changed by a reset operation. SV Access permitted in Supervisor Mode. R Read-only register. 32 Only ...
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CSA Context Save Area CSFR Core Special Function Register DAP Device Access Port DAS Device Access Server DCACHE Data Cache DFLASH Data Flash Memory DGPR Data General Purpose Register DMA Direct Memory Access DMI Data Memory Interface EBU External Bus ...
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NC Not Connected NMI Non-Maskable Interrupt OCDS On-Chip Debug Support OVRAM Overlay Memory PCP Peripheral Control Processor PMU Program Memory Unit PLL Phase Locked Loop PCODE PCP Code Memory PFLASH Program Flash Memory PMI Program Memory Interface PMU Program Memory ...
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System Architecture of the TC1797 The TC1797 combines three powerful technologies within one silicon die, achieving new levels of power, speed, and economy for embedded applications: • Reduced Instruction Set Computing (RISC) processor architecture • Digital Signal Processing (DSP) ...
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TC1797 Block Diagram Figure 1 shows the block diagram of the TC1797. PMI 24 KB SPRAM 32 KB SPRAM 16 KB ICACHE (Configurable ICACHE EBU PMU0 PMU1 2 MB PFlash 1 MB PFlash 64 KB DFlash 8 ...
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System Features The TC1797 has the following features: Package • P/PG-BGA-416-10 package, 1mm pitch Clock Frequencies for the 180 MHz derivative • Maximum CPU clock frequency: 180 MHz • Maximum PCP clock frequency: 180 MHz • Maximum system clock ...
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CPU Cores of the The TC1797 includes a high Performance CPU and a Peripheral Control Processor. 2.2.3.1 High-performance 32-bit CPU This chapter gives an overview about the TriCore 1 architecture. TriCore (TC1.3.1) Architectural Highlights • Unified RISC MCU/DSP • ...
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Kbyte Data Cache (DACHE) • On-chip SRAMs with parity error detection 2.2.3.2 High-performance 32-bit Peripheral Control Processor The PCP is a flexible Peripheral Control Processor optimized for interrupt handling and thus unloading the CPU. Features • Data move ...
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On-Chip System Units The TC1797 microcontroller offers several versatile on-chip system peripheral units such as DMA controller, embedded Flash module, interrupt system and ports. 2.3.1 Flexible Interrupt System The TC1797 includes a programmable interrupt system with the following features: ...
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Source and destination address register – Channel control and status register – Transfer count register • Flexible interrupt generation (the service request node logic for the MLI channel is also implemented in the DMA module) • DMA module is ...
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System Timer The TC1797’s STM is designed for global system timing applications requiring both high precision and long range. Features • Free-running 56-bit counter • All 56 bits can be read synchronously • Different 32-bit portions of the 56-bit ...
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Figure 2 provides an overview on the STM module. It shows the options for reading parts of STM content. to DMA etc. STM IRQ0 Interrupt STM Control IRQ1 Enable / Disable Clock f Control STM STM_TIM5 Address Decoder PORST Figure ...
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System Control Unit The following SCU introduction gives an overview about the TC1797 System Control Unit (SCU) For Information about the SCU see chapter 3. 2.3.4.1 Clock Generation Unit The Clock Generation Unit (CGU) allows a very flexible clock ...
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Trigger sources that need a clock in order to be asserted, such as the input signals ESR0, ESR1, the WDT trigger, the parity trigger, or the SW trigger. 2.3.4.4 External Interface The SCU provides interface pads for system purpose. ...
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The Boot ROM interface. • The Emulation Memory interface. • The Local Memory Bus LMB slave interface. Following memories are controlled by and belong to the PMU0: • 2 Mbyte of Program Flash memory (PFlash) • 64 Kbyte of ...
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The following figure shows the block diagram of the PMU0: PMU0 Overlay RAM Interface 64 OVRAM Emulation Memory Interface Emulation Memory (ED chip only ) Figure 3 PMU0 Basic Block Diagram As described before the PMU1 is reduced to the ...
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Overlay RAM and Data Acquisition The overlay memory OVRAM is provided in the PMU especially for redirection of data accesses to program memory to the OVRAM by using the data overlay function. The data overlay functionality itself is controlled ...
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In TC1797 the PMU1 contains 2 Mbyte of Program Flash realized as one Flash bank. It does not contain any Data Flash. Since in TC1797 the two PMUs can work in parallel, further combinations of concurrent operations are supported if ...
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Flash by the CPU, but may also be issued by the DMA controller (or OCDS). The Flash also features an advanced read/write protection architecture, including a read protection for the whole Flash array (optionally without Data Flash) ...
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Overlay support with SRAM for calibration applications. • Configurable wait state selection for different CPU frequencies. • Endurance = 1000; minimum 1000 program/erase cycles per physical sector; reduced endurance of 100 per 16 KB sector. • Operating lifetime (incl. ...
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Data Access Overlay The data overlay functionality provides the capability to redirect data accesses by the TriCore to program memory (internal Program Flash or external memory) to the Overlay SRAM in the PMU the Emulation Memory in ...
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Flexible Peripheral Interconnect Buses (FPI Bus) for on-chip interconnections and its FPI Bus control unit (SBCU) • The System Timer (STM) with high-precision, long-range timing capabilities • The TC1797 includes a power management system, a watchdog timer as well ...
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On-Chip Peripheral Units of the TC1797 The TC1797 microcontroller offers several versatile on-chip peripheral units such as serial controllers, timer units, and Analog-to-Digital converters. Several I/O lines on the TC1797 ports are reserved for these peripheral units to communicate ...
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Asynchronous/Synchronous Serial Interfaces The TC1797 includes two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. Both ASC modules have the same functionality. Figure 5 shows a global view of the Asynchronous/Synchronous Serial Interface (ASC). f Clock ASC Control Address Decoder EIR ...
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Features • Full-duplex asynchronous operating modes – 8-bit or 9-bit data frames, LSB first – Parity-bit generation/checking – One or two stop bits – Baud rate from 5.625 Mbit/s to 1.34 bit MHz module clock) – Multiprocessor mode ...
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High-Speed Synchronous Serial Interfaces The TC1797 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1. Both SSC modules have the same functionality. Figure 6 shows a global view of the Synchronous Serial interface (SSC). f SSC Clock f Control ...
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Features • Master and Slave Mode operation – Full-duplex or half-duplex operation – Automatic pad control possible • Flexible data format – Programmable number of data bits bits – Programmable shift direction: LSB or MSB shift first ...
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Micro Second Channel Interface The TC1797 includes two Micro Second Channel interfaces, MSC0 and MSC1. Both MSC modules have the same functionality. Each Micro Second Channel (MSC) interface provides serial communication links typically used to connect power switches or ...
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Features • Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses • High-speed synchronous serial transmission on downstream channel – Serial output clock frequency: – Fractional clock divider for precise frequency control ...
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... Infineon Technologies FlexRay Consortium. Data Sheet RXDA TXDA Channel A TXENA RXDB TXDB Channel B ERAY TXENB Module (Kernel) STPW MT ® , are trademarks of Infineon Technologies AG. FlexRay™ trademark of 39 TC1797 Introduction 1) protocol Port Control Stop Watch External Trigger Request Select Unit External Clock ...
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The E-Ray module communicates with the external world via three I/O lines each channel. The RXDAx and RXDBx lines are the receive data input signals, TXDA and TXDB lines are the transmit output signals, TXENA and TXENB the transmit enable ...
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Automatic delayed read access to Input Command Request Register (IBCR data transfer from Input Shadow Buffer to Message RAM to (initiated by a previous write access to the IBCR) is ongoing. • Four Input Buffer for building ...
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MultiCAN Controller The MultiCAN module provides four independent CAN nodes, representing four serial communication interfaces. The number of available message objects is 128. f CAN Clock f Control CLC Message Object Buffer Address Decoder Objects Interrupt Control Figure 9 ...
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Features • Compliant with ISO 11898 • CAN functionality according to CAN specification V2.0 B active • Dedicated control registers for each CAN node • Data transfer rates Mbit/s • Flexible and powerful message transfer control and ...
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interrupt output lines are available. Interrupt requests can be routed individually to one of the 16 interrupt output lines. – Message post-processing notifications can be combined flexibly into a dedicated register field of 256 notification bits. ...
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Micro Link Serial Bus Interface This TC1797 contains two Micro Link Serial Bus Interfaces, MLI0 and MLI1. The Micro Link Interface (MLI fast synchronous serial interface to exchange data between microcontrollers or other devices, such as stand-alone ...
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Figure 11 shows a general block diagram of the MLI module. f Fract. SYS Divider TR[3:0] BRKOUT Move SR[7:0] Engine Figure 11 General Block Diagram of the MLI Modules The MLI transmitter and MLI receiver communicate with other MLI receivers ...
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General Purpose Timer Array (GPTA) The TC1797 contains the General Purpose Timer Array (GPTA0), plus the additional Local Timer Cell Array (LTCA2). The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to ...
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Functionality of GPTA0 The General Purpose Timer Array (GPTA0) provides a set of hardware modules required for high-speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic units ...
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Mode, GPTA signal frequency in 3-sensor Mode • Duty Cycle Measurement (DCM) – Four independent units – 100% margin and time-out handling f – maximum resolution GPTA f – ...
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On-chip Trigger Unit • 16 on-chip trigger signals I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface 2.5.7.2 Functionality of LTCA2 The Local Timer Cell Array (LTCA2) provides a set of ...
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Analog-to-Digital Converters The TC1797 includes three Analog to Digital Converter modules (ADC0, ADC1, ADC2) and one Fast Analog to Digital Converter (FADC). 2.5.8.1 ADC Block Diagram The analog to digital converter module (ADC) allows the conversion of analog input ...
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Input voltage range from 0V to analog supply voltage • Analog supply voltage range from 3 (single supply) (5V nominal supply voltage, performance degradation accepted for lower voltages) • Input multiplexer width of 16 possible ...
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FADC Short Description General Features • Extreme fast conversion, 21 cycles of • 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter) • Successive approximation conversion method • Two differential ...
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As shown in Figure 14, the main FADC functional blocks are: • An Input Structure containing the differential inputs and impedance control. • An A/D Converter Stage responsible for the analog-to-digital conversion including an input multiplexer to select between the ...
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Analog Input Stages FAIN0P Rp FAIN0N Rn Rp FAIN2P FAIN2N Rn Rp FAIN1P FAIN1N Rn Rp FAIN3P FAIN3N DDIF Figure 15 FADC Input Structure in TC1797 Data Sheet Channel Amplifier Stages V DDMF V SSMF V DDMF ...
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External Bus Interface The External Bus Unit (EBU) of the TC1797 controls the accesses from peripheral units to external memories. Features: • 64-bit internal LMB interface • 32-bit demultiplexed / 16-bit multiplexed external bus interface (3.3V, 2.5V) – Support ...
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On-Chip Debug Support The classic software debug approach (start/stop, single-stepping) is supported by several features labelled “OCDS Level 1”: • Run/stop and single-step execution independently for TriCore and PCP. • Means to request all kinds of reset without usage ...
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Changing the configuration is triggered by a single SFR access to maintain consistency. • Overlay configuration switch does not require the TriCore to be stopped or suspended. • Invalidation of the Data Cache (maintaining write-back data) can be done ...
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SSCM (Single Scan Chain Mode 1) This function requires access to some device pins (e.g. TESTMODE) in addition to those needed for OCDS. Data Sheet 1) ) for structural scan testing of the chip itself. 59 TC1797 Introduction V1.1, ...
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Pinning 3.1 TC1797 Pin Definition and Functions: P/PG-BGA-416-10 Figure 16 is showing the TC1797 Logic Symbol for the package variant: P/PG-BGA-416-10. PORST TESTMODE General Control ESR0 ESR1 TRST TCK / DAP0 TDI / BRKIN/ OCDS / BRKOUT JTAG Control ...
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TC1797 P/PG-BGA-416-10 Package Variant Pin Configuration Figure 17 shows the TC1797 pin configuration for the P/PG-BGA-416-10 package variant N.C. P2.9 P2.13 P2.15 P0.14 P0.5 P0.2 B P2.6 P2.7 P2.10 P2.14 P0.9 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) Pin Symbol Ctrl. Port 0 A9 P0.0 I/O0 HWCFG0 I OUT56 O1 OUT56 O2 OUT80 O3 A8 P0.1 I/O0 HWCFG1 I OUT57 O1 OUT57 O2 OUT81 O3 A7 P0.2 I/O0 HWCFG2 I ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B7 P0.4 I/O0 HWCFG4 I OUT60 O1 OUT60 O2 OUT84 O3 A6 P0.5 I/O0 HWCFG5 I OUT61 O1 OUT61 O2 OUT85 O3 B6 P0.6 I/O0 HWCFG6 I OUT62 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B5 P0.9 I/O0 RXDA0 I Reserved O1 Reserved O2 Reserved O3 C6 P0.10 I/O0 TXENA O1 Reserved O2 Reserved O3 D6 P0.11 I/O0 TXENB O1 Reserved O2 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. A5 P0.14 I/O0 TXDA O1 Reserved O2 Reserved O3 D4 P0.15 I/O0 Reserved O1 Reserved O2 Reserved O3 Port 1 P3 P1.0 I/O0 REQ0 I EXTCLK1 O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. N1 P1.3 I/O0 REQ3 I TREADY0B I Reserved O1 Reserved O2 Reserved O3 N4 P1.4 I/O0 TCLK0 O1 Reserved O2 Reserved O3 M4 P1.5 I/O0 TREADY0A I Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. M3 P1.8 I/O0 RCLK0A I OUT64 O1 OUT64 O2 OUT88 O3 M2 P1.9 I/O0 RREADY0A O1 SLSO11 O2 OUT65 O3 M1 P1.10 I/O0 RVALID0A I OUT66 O1 OUT66 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. L3 P1.13 I/O0 RCLK0B I OUT69 O1 OUT69 O2 OUT93 O3 L2 P1.14 I/O0 RVALID0B I OUT70 O1 OUT70 O2 OUT94 O3 L1 P1.15 I/O0 RData0B I OUT70 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. D2 P2.3 I/O0 SLSO03 O1 SLSO13 O2 SLSO03 O3 AND SLSO13 D1 P2.4 I/O0 SLSO04 O1 SLSO14 O2 SLSO04 O3 AND SLSO14 C1 P2.5 I/O0 SLSO05 O1 SLSO15 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B2 P2.7 I/O0 SLSO07 O1 SLSO17 O2 SLSO07 O3 AND SLSO17 C2 P2.8 I/O0 IN0 I IN0 I IN0 I OUT0 O1 OUT0 O2 OUT0 O3 A2 P2.9 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B3 P2.10 I/O0 IN2 I IN2 I IN2 I OUT2 O1 OUT2 O2 OUT2 O3 C3 P2.11 I/O0 IN3 I IN3 I IN3 I OUT3 O1 OUT3 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. A3 P2.13 I/O0 IN5 I IN5 I IN5 I OUT5 O1 OUT5 O2 OUT5 O3 B4 P2.14 I/O0 IN6 I IN6 I IN6 I OUT6 O1 OUT6 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B12 P3.0 I/O0 IN8 I IN8 I IN8 I OUT8 O1 OUT8 O2 OUT8 O3 A12 P3.1 I/O0 IN9 I IN9 I IN9 I OUT9 O1 OUT9 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B11 P3.3 I/O0 IN11 I IN11 I IN11 I OUT11 O1 OUT11 O2 OUT11 O3 C12 P3.4 I/O0 IN12 I IN12 I IN12 I OUT12 O1 OUT12 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B10 P3.6 I/O0 IN14 I IN14 I IN14 I OUT14 O1 OUT14 O2 OUT14 O3 C9 P3.7 I/O0 IN15 I IN15 I IN15 I OUT15 O1 OUT15 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. C11 P3.9 I/O0 IN17 I IN17 I IN17 I OUT17 O1 OUT17 O2 OUT17 O3 C10 P3.10 I/O0 IN18 I IN18 I IN18 I OUT18 O1 OUT18 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. D11 P3.12 I/O0 IN20 I IN20 I IN20 I OUT20 O1 OUT20 O2 OUT20 O3 D12 P3.13 I/O0 IN21 I IN21 I IN21 I OUT21 O1 OUT21 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B9 P3.15 I/O0 IN23 I IN23 I IN23 I OUT23 O1 OUT23 O2 OUT23 O3 Port 4 AD10 P4.0 I/O0 IN24 I IN24 I IN24 I OUT24 O1 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AD11 P4.2 I/O0 IN26 I IN26 I IN26 I OUT26 O1 OUT26 O2 OUT26 O3 AE11 P4.3 I/O0 IN27 I IN27 I IN27 I OUT27 O1 OUT27 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AD12 P4.5 I/O0 IN29 I IN29 I IN29 I OUT29 O1 OUT29 O2 OUT29 O3 AF10 P4.6 I/O0 IN30 I IN30 I IN30 I OUT30 O1 OUT30 O2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AC13 P4.8 I/O0 IN32 I IN32 I OUT32 O1 OUT32 O2 OUT0 O3 AF11 P4.9 I/O0 IN33 I IN33 I OUT33 O1 OUT33 O2 OUT1 O3 AF12 P4.10 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AC14 P4.12 I/O0 IN36 I IN36 I OUT36 O1 OUT36 O2 OUT4 O3 AE13 P4.13 I/O0 IN37 I IN37 I OUT37 O1 OUT37 O2 OUT5 O3 AF13 P4.14 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. B13 P5.0 I/O0 RXD0A I RXD0A O1 OUT72 O2 OUT72 O3 A13 P5.1 I/O0 TXD0 O1 OUT73 O2 OUT73 O3 A14 P5.2 I/O0 RXD1A I RXD1A O1 OUT74 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. C14 P5.5 I/O0 SDI0 I OUT77 O1 OUT77 O2 OUT101 O3 B15 P5.6 I/O0 EN10 O1 TVALID0B O2 OUT78 O3 A15 P5.7 I/O0 SDI1 I OUT79 O1 OUT79 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. C17 P5.10 I/O0 FCLN0 O1 OUT82 O2 OUT82 O3 C18 P5.11 I/O0 FCLP0A O1 OUT83 O2 OUT83 O3 A16 P5.12 I/O0 SON1 O1 OUT84 O2 OUT84 O3 B16 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. A17 P5.15 I/O0 FCLNP1A O1 OUT87 O2 OUT87 O3 Port 6 F3 P6.4 I/O0 MTSR1 I MTSR1 O1 Reserved O2 Reserved O3 G4 P6.5 I/O0 MRST1 I MRST1 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. G3 P6.7 I/O0 SLSI11 I Reserved O1 Reserved O2 Reserved O3 F4 P6.8 I/O0 RXDCAN0 I RXD0B I Reserved O1 RXD0B O2 Reserved O3 E4 P6.9 I/O0 TXDCAN0 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. E2 P6.11 I/O0 TXDCAN1 O1 TXD1 O2 TXENB O3 E1 P6.12 I/O0 RXDCAN2 I RXDA1 I Reserved O1 Reserved O2 Reserved O3 G2 P6.13 I/O0 TXDCAN2 O1 TXDA ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. Port 7 R3 P7.0 I/O0 REQ4 I AD2EMUX2 O1 Reserved O2 Reserved O3 R2 P7.1 I/O0 REQ5 I AD0EMUX2 O1 Reserved O2 Reserved O3 U4 P7.2 I/O0 AD0EMUX0 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. T2 P7.5 I/O0 REQ7 I AD2EMUX1 O1 Reserved O2 Reserved O3 T1 P7.6 I/O0 AD1EMUX0 O1 Reserved O2 Reserved O3 U2 P7.7 I/O0 AD1EMUX1 O1 Reserved O2 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. H1 P8.1 I/O0 IN41 I IN41 I TREADY1A I OUT41 O1 OUT41 O2 Reserved O3 J3 P8.2 I/O0 IN42 I IN42 I OUT42 O1 OUT42 O2 TVALID1A O3 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. K2 P8.5 I/O0 IN45 I IN45 I OUT45 O1 OUT45 O2 RREADY1A O3 K3 P8.6 I/O0 IN46 I IN46 I RVALID1A I OUT46 O1 OUT46 O2 Reserved O3 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. A19 P9.0 I/O0 IN48 I IN48 I OUT48 O1 OUT48 O2 EN12 O3 B19 P9.1 I/O0 IN49 I IN49 I OUT49 O1 OUT49 O2 EN11 O3 B20 P9.2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. D18 P9.4 I/O0 IN52 I IN52 I OUT52 O1 OUT52 O2 EN03 O3 ’D19 P9.5 I/O0 IN53 I IN53 I OUT53 O1 OUT53 O2 EN02 O3 C19 P9.6 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. C20 P9.8 I/O0 FCLP0B O1 FCLP0B O2 FCLP0B O3 A21 P9.9 I/O0 Reserved O1 Reserved O2 Reserved O3 B21 P9.10 I/O0 EMGSTOP I Reserved O1 Reserved O2 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. C26 P9.13 I/O0 BRKIN I Reserved O1 Reserved O2 Reserved O3 BRKOUT O D26 P9.14 I/O0 BRKIN I Reserved O1 Reserved O2 Reserved O3 BRKOUT O Port 10 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AD15 P10.2 I/O0 SLSI01 I Reserved O1 Reserved O2 Reserved O3 AF14 P10.3 I/O0 SCLK0 I SCLK0 O1 Reserved O2 Reserved O3 AE14 P10.4 I/O0 SLSO00 O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. K25 P11.1 I/O0 Reserved O1 Reserved O2 Reserved K26 P11.2 I/O0 Reserved O1 Reserved O2 Reserved J23 P11.3 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. L26 P11.6 I/O0 Reserved O1 Reserved O2 Reserved K23 P11.7 I/O0 Reserved O1 Reserved O2 Reserved M26 P11.8 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. L24 P11.11 I/O0 Reserved O1 Reserved O2 Reserved O3 A11 O N26 P11.12 I/O0 Reserved O1 Reserved O2 Reserved O3 A12 O N23 P11.13 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. P26 P12.0 I/O0 Reserved O1 Reserved O2 Reserved O3 A16 O P24 P12.1 I/O0 Reserved O1 Reserved O2 Reserved O3 A17 O P25 P12.2 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. R25 P12.5 I/O0 Reserved O1 Reserved O2 Reserved O3 A21 O J24 P12.6 I/O0 Reserved O1 Reserved O2 Reserved O3 A22 O J25 P12.7 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. T24 P13.1 I/O0 AD1 I OUT89 O1 OUT89 O2 OUT81 O3 AD1 O U26 P13.2 I/O0 AD2 I OUT90 O1 OUT90 O2 OUT82 O3 AD2 O T25 P13.3 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. U25 P13.5 I/O0 AD5 I OUT93 O1 OUT93 O2 OUT85 O3 AD5 O U23 P13.6 I/O0 AD6 I OUT94 O1 OUT94 O2 OUT86 O3 AD6 O W26 P13.7 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. U24 P13.9 I/O0 AD9 I OUT97 O1 OUT97 O2 OUT89 O3 AD9 O Y26 P13.10 I/O0 AD10 I OUT98 O1 OUT98 O2 OUT90 O3 AD10 O AA26 P13.11 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. V24 P13.13 I/O0 AD13 I OUT101 O1 OUT101 O2 OUT93 O3 AD13 O Y25 P13.14 I/O0 AD14 I OUT102 O1 OUT102 O2 OUT94 O3 AD14 O AB26 P13.15 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AA25 P14.1 I/O0 AD17 I OUT97 O1 OUT97 O2 OUT97 O3 AD17 O Y24 P14.2 I/O0 AD18 I OUT98 O1 OUT98 O2 OUT98 O3 AD18 O AA23 P14.3 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AB24 P14.5 I/O0 AD21 I OUT101 O1 OUT101 O2 OUT101 O3 AD21 O AA24 P14.6 I/O0 AD22 I OUT102 O1 OUT102 O2 OUT102 O3 AD22 O AC26 P14.7 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AC25 P14.9 I/O0 AD25 I OUT105 O1 OUT105 O2 OUT105 O3 AD25 O AE26 P14.10 I/O0 AD26 I OUT106 O1 OUT106 O2 OUT106 O3 AD26 O AD25 P14.11 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AE25 P14.13 I/O0 AD29 I OUT109 O1 OUT109 O2 OUT109 O3 AD29 O AE24 P14.14 I/O0 AD30 I OUT110 O1 OUT110 O2 OUT110 O3 AD30 O AD24 P14.15 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AD21 P15.1 I/O0 Reserved O1 Reserved O2 Reserved O3 CS1 O AD20 P15.2 I/O0 Reserved O1 Reserved O2 Reserved O3 CS2 O AD19 P15.3 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AF18 P15.6 I/O0 Reserved O1 Reserved O2 Reserved O3 BC2 O AE18 P15.7 I/O0 Reserved O1 Reserved O2 Reserved O3 BC3 O AF20 P15.8 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AE20 P15.11 I/O0 WAIT I Reserved O1 Reserved O2 Reserved O3 AF19 P15.12 I/O0 Reserved O1 Reserved O2 Reserved O3 MR/W O AF23 P15.13 I/O0 Reserved O1 Reserved ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. Port 16 AF17 P16.0 I/O0 HOLD I Reserved O1 Reserved O2 Reserved O3 AD18 P16.1 I/O0 HLDA I Reserved O1 Reserved O2 Reserved O3 HLDA O AD22 P16.2 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AB3 AN3 I AC2 AN4 I AA3 AN5 I AD1 AN6 I AB4 AN7 I AC1 AN8 I AB2 AN9 I Y3 AN10 I AA2 AN11 I AB1 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AF6 AN29 I AE7 AN30 I AF7 AN31 I AC3 AN32 I AE2 AN33 I AD3 AN34 I AD5 AN35 I AE3 AN36 I AF2 AN37 I AC4 ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. E25 TDI I BRKIN I BRKOUT O B23 TESTMODE I F24 TMS I DAP1 I/O TRST F23 I G26 XTAL1 I G25 XTAL2 O D25 TDO O BRKIN ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AF5 V - AGND0 V - AGND2 V AD6 - AREF1 V AC6 - AGND1 AD9 V - AREF2 V AF8 - FAREF V AE8 - FAGND V ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AC11 AC20, AB23, V23, P23, E23, D24, C25, B26, D16, D9, H4 AC16, - DDP AD16, AE16, AF16, D22, C23, B24, A25, D14, ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. AC10 AC17, AC19, AC23, W23, R23, L23, D23, C24, B25, A26, D15, D8, J4, T4 K10 K11, K12, K13, K14, K15, K16, ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. N10 N11, N12, N13, N14, N15, N16, N17 V P10 P11, P12, P13, P14, P15, P16, P17 V R10 R11, R12, ...
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Table 4 Pin Definitions and Functions (BGA-416 Package) (cont’d) Pin Symbol Ctrl. U10 U11, U12, U13, U14, U15, U16, U17 1) This pin is also connected to the analog power supply for comparator of the ADC module. ...
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Table 5 List of Pull-Up/Pull-Down Reset Behavior of the Pins Pins ESR0 ESR1 TDO 1) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter for details. 2) See the SCU_IOCR register description. ...
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Identification Registers The Identification Registers uniquely identify a module or the whole device. Table 4-1 TC1797 Identification Registers Short Name Value ADC0_ID 0059 C000 ADC1_ID 0059 C000 ADC2_ID 0059 C000 ASC0_ID 0000 4402 ASC1_ID 0000 4402 CAN_ID 002B C051 ...
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Table 4-1 TC1797 Identification Registers (cont’d) Short Name Value MSC1_ID 0028 C003 PCP_ID 0020 C006 PMI_ID 000B C005 PMU0_ID 0050 C001 PMU1_ID 0051 C001 SBCU_ID 0000 6A0C SCU_CHIPID 0000 9001 SCU_ID 0052 C001 SCU_MANID 0000 1820 SCU_RTID 0000 0003 SSC0_ID ...
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Electrical Parameters 5.1 General Parameters 5.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the TC1797 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a ...
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Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in the Table 6 Pad Driver and Pad Classes Overview Class ...
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Absolute Maximum Ratings Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated ...
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Table 7 Absolute Maximum Rating Parameters Parameter PCP Frequency E-Ray Sample Frequency 1) Applicable for DDOSC Applicable for , , DDP DDEBU 5.1.4 Operating Conditions The following operating conditions must ...
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Table 8 Operating Condition Parameters Parameter Analog supply voltages – Overload current at class D pins Sum of overload current at class D pins Overload coupling 5) factor for analog inputs CPU & LMB Bus Frequency PCP Frequency FPI Bus ...
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See additional document “TC1767 Pin Reliability in Overload“ for definition of overload current on digital pins. 5) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to the resulting leakage ...
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Table 9 Pin Groups for Overload / Short-Circuit Current Sum Parameter Group Pins 21 P9.[14:13, 10:9] 22 P9.[12:11, 8: P9.[6: P9.[0, 4], P5.[10, 11] 25 P5.[15:14, 9:8] 26 P5.[13:12 P5.[7: ...
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DC Parameters 5.2.1 Input/Output Pins Table 10 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol General Parameters 1) I Pull-up current | | PUH I Pull-down | | PDL 1) current 1) C Pin capacitance IO (Digital I/O) V Input ...
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Table 10 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol t Spike filter always SF1 blocked pulse duration t Spike filter pass- SF2 through pulse duration Class A Pads ( V = 3. 3.3V ± 5%) DDP ...
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Table 10 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol I Input leakage OZA2 current Class A2 pins Input leakage I OZA1 current Class A1 pins V Class B Pads ( = 2.375 to 3.47 V) DDEBU Output low voltage V ...
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Table 10 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol Class F Pads, CMOS Mode ( V Input low voltage ILF Class F pins V Input high voltage IHF Class F pins Input hysteresis HYSF Class F pins Input leakage I ...
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Analog to Digital Converters (ADC0/ADC1/ADC2) All ADC parameters are optimized for and valid in the range of Table 11 ADC Characteristics (Operating Conditions apply) Parameter Symbol Analog supply V DDM voltage Analog ground SSM voltage V ...
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Table 11 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol 9)5) Gain error EA GAIN 9)5) Offset error EA OFF I Input leakage CC OZ1 current at analog inputs of ADC0/1 11) 12) 13) I Input leakage OZ2 current at ...
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Table 11 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol C Switched AINSW capacitance at the analog voltage inputs R ON resistance of AIN the transmission gates in the analog voltage path R ON resistance AIN7T for the ADC test ...
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Only one of these parameters is tested, the other is verified by design characterization. 13) The leakage current decreases typically 30% for junction temperature decrease of 10oC. I 14) is valid for the minimum specified conversion time. The current ...
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R EXT AIN EXT V Figure 19 ADC0/ADC1 Input Circuits ...
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Fast Analog to Digital Converter (FADC) All parameters apply to FADC used in differential mode, which is the default and the intended mode of operation, and which takes advantage of many error cancelation effects inherent to differential measurements in ...
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Table 13 FADC Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol t Conversion time C f Converter Clock FADC R Input resistance of FAIN the analog voltage path (Rn, Rp) f Channel Amplifier COFF 9) Cutoff Frequency t Settling Time of ...
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FAINxN V FAGND FAINxP V V FAREF V Figure 21 FADC Input Circuits Data Sheet FADC Analog Input Stage FAREF R P FADC Reference Voltage Input Circuitry FAREF I FAREF FAGND 144 Electrical Parameters - + /2 ...
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Oscillator Pins Table 14 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol f Frequency Range OSC V Input low voltage at ILX 1) XTAL1 V Input high voltage at IHX 1) XTAL1 Input current at I IX1 XTAL1 1) ...
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The following formula calculates the temperature measured by the DTS in [ RESULT bitfield of the DTSSTAT register. Data Sheet DTSSTAT RESULT Tj = ----------------------------------------------------------------- - 146 TC1797 Electrical Parameters o C] from the 619 – V1.1, ...
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Power Supply Current The default test conditions (differences explicitly specified) are: VDD=1.58 V, VDD=3.47 V, fCPU=180 MHz, Tj=150oC Table 16 Power Supply Currents (Operating Conditions apply) Parameter Core active mode 1)2) 3) supply current Realistic core active 4) 5) ...
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Not using the E-Ray module, E-Ray PLL in an application lowers the current consumption for typically 9mA. 4) The I decreases by typically the DD Realistic Pattern. The dependency in this range is, at constant junction ...
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AC Parameters All AC parameters are defined with the temperature compensation disabled. That means, keeping the pads constantly at maximum strength. 5.3.1 Testing Waveforms V DDP V DDEBU 10 Figure 22 Rise/Fall Time Parameters V DDP V ...
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Output Rise/Fall Times Table 17 Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Class A1 Pads Rise/fall times , RA1 FA1 Class A2 Pads t t Rise/fall times , RA2 FA2 1) Class B Pads 3.3V ...
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Power Sequencing V 5V 3.3V 1.5V V DDP Figure 3 1.5 V Power-Up/Down Sequence The following list of rules applies to the power-up/down sequence: • All ground pins V must be externally connected ...
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VDDP ), are internally directly connected recommended that the power pins of the same voltage are driven by a single power supply. • The PORST signal may be deactivated after all VDD5, VDD3.3, VDD1.5, and VAREF power-supplies ...
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Power, Pad and Reset Timing Table 18 Power, Pad and Reset Timing Parameters Parameter V Min. voltage to ensure DDP 1) defined pad states 2) Oscillator start-up time Minimum PORST active time after power supplies are stable at operating ...
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Applicable for input pins TESTMODE and TRST FPI CPU 6) Not subject to production test, verified by design / characterization. 7) This parameter includes the delay of the analog spike filter in the PORST ...
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Phase Locked Loop (PLL) Note: All PLL characteristics defined on this and the next page are not subject to production test, but verified by design characterization. Table 19 PLL Parameters (Operating Conditions apply) Parameter Accumulated jitter VCO frequency range ...
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With rising number of clock cycles the maximum jitter increases linearly value m of that is defined by the K2-factor of the PLL. Beyond this value of accumulated jitter remains at a constant value. Further, a ...
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KHz. These conditions can be achieved by appropriate blocking of the supply voltage as near as possible to the supply pins and using PCB supply and ground planes. Data Sheet Electrical Parameters 157 TC1797 V1.1, 2009-04 ...
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E-Ray Phase Locked Loop (E-Ray PLL) Note: All PLL characteristics defined on this and the next page are not subject to production test, but verified by design characterization. Table 20 PLL Parameters of the System PLL(Operating Conditions apply) Parameter ...
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BFCLKO Output Clock Timing 1.5 V ± 5 -40 °C to +125 ° Table 21 BFCLK0 Output Clock Timing Parameters Parameter BFCLKO clock period BFCLKO high time ...
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JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test but verified by design and/or characterization. Table ...
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V 0 Figure 29 Test Clock Timing (TCK) TCK TMS TDI t 9 TDO Figure 30 JTAG Timing Data Sheet 161 ...
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DAP Interface Timing The following parameters are applicable for communication through the DAP debug interface. Note: These parameters are not subject to production test but verified by design and/or characterization. Table 23 DAP Interface Timing Parameters (Operating Conditions apply) ...
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DAP0 DAP1 Figure 32 DAP Timing Host to Device DAP1 Figure 33 DAP Timing Device to Host Data Sheet Electrical Parameters 163 TC1797 MC_ DAP1_RX MC_ DAP1_TX V1.1, ...
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EBU Timings 1.5 V ± 5 -40 °C to +125 ° 5.3.10.1 EBU Asynchronous Timings For each timing, the accumulated PLL jitter of the programed duration in ...
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Read Timings Table 25 Asynchronous read timings, multiplexed and demultiplexed Parameter A(23:0) output delay A(23:0) output delay CS rising edge ADV rising edge BC rising edge WAIT input setup WAIT input hold Data input setup Data input hold MR / ...
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Multiplexed Read Timing Address EBU Phase STATE Control Bitfield: ADDRC Duration Limits in 1...15 EBU_CLK Cycles A[23:0] CS[3:0] CSCOMB ADV RD BC[3:0] WAIT Address Out AD[31:0] MR programmed value, T ...
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Demultiplexed Read Timing Address EBU Phase STATE Control Bitfield: ADDRC Duration Limits in 1...15 EBU_CLK Cycles A[23:0] CS[3:0] CSCOMB pv + ADV RD BC[3:0] WAIT AD[31:0] MR programmed value sum (correponding bitfield values) EBU_CLK Figure 35 ...
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Write Timings Table 26 Asynchronous write timings, multiplexed and demultiplexed Parameter A(23:0) output delay to RD/WR rising edge, deviation from the ideal A(23:0) output delay programmed value. CS rising edge ADV rising edge BC rising edge WAIT input setup WAIT ...
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Multiplexed Write Timing Address EBU Phase STATE Control Bitfield: ADDRC Duration Limits in 1...15 EBU_CLK Cycles A[23:0] CS[3:0] CSCOMB ADV RD/WR BC[3:0] WAIT AD[31:0] Address Out MR programmed value, T ...
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Demultiplexed Write Timing Address EBU Phase STATE Control Bitfield: ADDRC Duration Limits in 1...15 EBU_CLK Cycles A[23:0] CS[3:0] CSCOMB ADV RD/WR BC[3:0] WAIT AD[31:0] MR programmed value sum (correponding bitfield values) EBU_CLK ...
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EBU Burst Mode Access Timing 1.5 V ± 5 -40 °C to +125 ° Table 27 EBU Burst Mode Read / Write Access Timing Parameters Parameter Output ...
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If the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as at asynchronous access. So t5, t6, t7 and t8 from the asynchronous timings apply. Address Phase(s) BFCLKI 1) ...
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EBU Arbitration Signal Timing 1.5 V ± 5 -40°C to +125 ° Table 28 EBU Arbitration Signal Timing Parameters Parameter Output delay from BFCLKO rising edge Data ...
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Peripheral Timings Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization. 5.3.11.1 Micro Link Interface (MLI) Timing MLI Transmitter Timing t TCLKx TDATAx TVALIDx TREADYx MLI Receiver Timing t RCLKx RDATAx RVALIDx RREADYx ...
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Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Table 29 MLI Timings (Operating Conditions apply), C Parameter MLI Transmitter Timing TCLK clock period TCLK high time ...
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The min./max. TCLK low/high times regarded additionally For high-speed MLI interface, strong driver sharp or medium edge selection (class A2 pad) is recommended for TCLK. 5) The following formula is valid: 6) The ...
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Micro Second Channel (MSC) Interface Timing Table 30 MSC Interface Timing (Operating Conditions apply), C Parameter 1)2) FCLP clock period SOP/ENx outputs delay from FCLP rising edge SDI bit time SDI rise time SDI fall time 1) FCLP signal ...
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SSC Master/Slave Mode Timing Table 31 SSC Master/Slave Mode Timing (Operating Conditions apply), C Parameter Master Mode Timing SCLK clock period MTSR/SLSOx delay from SCLK rising edge MRST setup to SCLK falling edge MRST hold from SCLK falling edge ...
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SCLK 1) MTSR 1) MRST 2) SLSOx 1) This timing is based on the following setup: CON.PH = CON. The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK ...
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E-Ray Interface Timing The timings in this section are valid for the strong / sharp and strong / medium settings of the output drivers, and for both input pads. The timing parameters are not subject to ...
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Bus Driver of dRxSlope ≤ 5 ns, 20% × 80% × , according to the FlexRay Electrical Physical Layer Specification V2.1 B. For V DDP A1 pads, the rise and fall times of the ...
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Package and Reliability 5.4.1 Package Parameters Table 33 Thermal Characteristics of the Package Device Package TC1797 P/PG-BGA-416-10 1) The top and bottom thermal resistances between the case and the ambient ( with the thermal resistances between the junction and ...
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Package Outline A26 Figure 45 Package Outlines P/PG-BGA-416-10, Plastic (Green) Ball Grid Array Data Sheet 416x +0.07 ø0.63 -0.13 ø0. ø0 ±0.2 24 ±0.5 27 ±0.2 ...
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You can find all of our packages, sorts of packing and others in Infineon Internet Page. 5.4.3 Flash Memory Parameters The data retention time of the TC1797’s Flash memory (i.e. the time after which stored data can still be retrieved) ...
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Quality Declarations Table 35 Quality Parameters Parameter Symbol Operation Lifetime V ESD susceptibility HBM according to Human Body Model (HBM) V ESD susceptibility HBM1 of the LVDS pins V ESD susceptibility CDM according to Charged Device ...
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