SI4704-D60-GM Silicon Laboratories Inc, SI4704-D60-GM Datasheet

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SI4704-D60-GM

Manufacturer Part Number
SI4704-D60-GM
Description
IC FM RADIO TUNER 20-QFN
Manufacturer
Silicon Laboratories Inc
Series
-r
Datasheet

Specifications of SI4704-D60-GM

Frequency
64MHz ~ 108MHz
Sensitivity
-
Data Rate - Maximum
-
Modulation Or Protocol
FM
Applications
General Purpose
Current - Receiving
10.5mA
Data Interface
PCB, Surface Mount
Memory Size
-
Antenna Connector
PCB, Surface Mount
Features
RSSI Equipped
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Package / Case
20-UFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI4704-D60-GMR
0
B
Features
Applications
Description
The Si4704/05-D60 digital CMOS FM radio receiver IC integrates the complete
tuner function from antenna input to digital audio output and includes a stereo
audio AUXIN ADC input for converting analog audio into standard I
audio, enabling a cost efficient digital audio platform for consumer electronic
applications with high TDMA noise immunity, superior radio performance, and
high fidelity audio power amplification. When enabling the analog inputs in stereo
AUXIN ADC-mode, the Si4704/05-D60 supports I
analog output).
Functional Block Diagram
Rev. 1.0 4/11
Worldwide FM band support
(64–108 MHz)
Excellent real-world performance
Integrated VCO
Advanced FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Digital FM stereo decoder
Programmable de-emphasis
Advanced Audio Processing
Multiplexed stereo audio AUXIN
ADC with 85 dB dynamic range
Table and portable radios
Mini/micro systems
CD/DVD and Blu-ray players
Stereo boom boxes
ROADCAST
2.7~5.5 V (QFN) / 2.0~5.5 V (SSOP)
FM Antenna
+
32.768 kHz
RFGND
RIN
LIN
RCLK
GND
FMI
VA
F M R
LNA
AFC
LDO
AGC
0/90
Mux
Copyright © 2011 by Silicon Laboratories
ADIO
Mux
FM digital tuning
EN55020 compliant
No manual alignment necessary
Programmable reference clock
Adjustable soft mute control
RDS/RBDS processor (Si4705-D60)
Digital audio out
2-wire and 3-wire control interface
Integrated LDO regulator
QFN and SSOP packages

Modules for consumer electronics
Clock radios
Mini HiFi and docking stations
Entertainment systems
RoHS compliant
ADC
ADC
2
S digital audio output only (no
Si4704/05-D60
(Si4705)
LOW-IF
RDS
DSP
R
INTERFACE
CONTROL
ECEIVER WITH
DIGITAL
AUDIO
DAC
DAC
DOUT
DFS
GPO/DCLK
ROUT
LOUT
VD
1.62 - 3.6 V
2
S digital
Si4704/05-D60
This product, its features, and/or its
architecture is covered by one or more of
the following patents, as well as other
patents, pending and issued, both
foreign
7,272,373;
7,355,476;
7,339,503; 7,339,504.
GPO3/[DCLK]
DOUT/[RIN]
R D S / R B D S
GPO2/[INT]
DFS/[LIN]
RFGND
Ordering Information:
Si4704/05-D60 (SSOP)
GPO1
RFGND
Si4704/05-D60 (QFN)
FMI
NC
NC
NC
LPI
NC
RST
FMI
NC
LPI
and
Pin Assignments
2
3
4
5
1
6
See page 29.
10
11
12
1
2
3
4
5
6
7
8
9
20
7,272,375;
7,426,376;
7
19
domestic:
GND
8
PAD
18
9
17
10
16
11
15 DOUT/[RIN]
14
13
12
24
23
22
21
20
19
18
17
16
15
14
13
Si4704/05-D60
LOUT/[DFS]
ROUT/[DOUT]
GND
VA
ROUT/[DOUT]
DBYP
VA
LOUT/[DFS]
VD
RCLK
SDIO
SCLK
SEN
RST
GND
GND
7,127,217;
7,321,324;
7,471,940;

Related parts for SI4704-D60-GM

SI4704-D60-GM Summary of contents

Page 1

... Stereo boom boxes  Description The Si4704/05-D60 digital CMOS FM radio receiver IC integrates the complete tuner function from antenna input to digital audio output and includes a stereo audio AUXIN ADC input for converting analog audio into standard I audio, enabling a cost efficient digital audio platform for consumer electronic applications with high TDMA noise immunity, superior radio performance, and high fidelity audio power amplification ...

Page 2

... Si4704/05-D60 2 Rev. 1.0 ...

Page 3

... Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1. Si4704/05-D60- 5.2. Si4704/05-D60- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 7.1. Si4704/05-D60 Top Mark (QFN 7.2. Top Mark Explanation (QFN 7.3. Si4704/05-D60 Top Mark (SSOP 7.4. Top Mark Explanation (SSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1. Si4704/05-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2. Si4704/05-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Si4704/05-D60 Rev. 1.0 ...

Page 4

... Si4704/05-D60 9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 9.1. Si4704/05-D60 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2. Si4704/05-D60 SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document Change List .39 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4 Rev. 1.0 ...

Page 5

... Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4704/05-D60 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. ...

Page 6

... Si4704/05-D60 Table 3. DC Characteristics (V = 2 1. Parameter FM Mode V Supply Current AQFN V Supply Current DQFN V Supply Current ASSOP V Supply Current DSSOP V Supply Current AQFN V Supply Current DQFN V Supply Current ASSOP V Supply Current DSSOP AUXIN Mode V Supply Current AQFN V Supply Current ...

Page 7

... Figure 1. Reset Timing Parameters for Busmode Select 1,2,3 = – °C) Symbol  t SRST t HRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then SRST t t HRST SRST 70% RST 30% 70% 30% 70% INT 30% Rev. 1.0 Si4704/05-D60 Min Typ Max Unit 100 — — µs 30 — — ...

Page 8

... RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4704/05-D60 delays SDIO by a minimum of 300 ns from the V t specification. ...

Page 9

... Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and Write Timing Diagram HIGH t r:IN f: HD:DAT SU:DAT D7-D0 ACK DATA ACK Rev. 1.0 Si4704/05-D60 t t SU:STO BUF t f:IN, STOP START t f:OUT D7-D0 DATA ACK STOP 9 ...

Page 10

... Si4704/05-D60 Table 6. 3-Wire Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to SCLKHold  Hold SEN Input to SCLK SCLKto SDIO Output Valid SCLK ...

Page 11

... DOUT t Figure 6. Digital Audio Interface Timing Parameters – °C) Symbol Test Condition t DCT t DCH t DCL t SU:DFS t HD:DFS t PD:DOUT t DCL t DCT t HD:DFS PD:OUT Rev. 1.0 Si4704/05-D60 Min Typ Max 26 — 1000 10 — — 10 — — 5 — — 5 — — 0 — SU:DFS 2 S Mode ...

Page 12

... Si4704/05-D60 Table 8. FM Receiver Characteristics (V = 2 1. Parameter Input Frequency 3,4,5,6 Sensitivity 6,7 RDS Sensitivity 7,8 LNA Input Resistance 7,8 LNA Input Capacitance 7,9 Input IP3 3,4,7,8 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity 7 Spurious Response Rejection 3,4,8 Audio Output Voltage ...

Page 13

... MHz, ±8 MHz R Single-ended L C Single-ended L RCLK tolerance = 100 ppm From powerdown Input levels of 8 and 60 dBµ Input . AGC is disabled. Rev. 1.0 Si4704/05-D60 Min Typ Max Unit — 40 — dBµV — 35 — dBµV 10 — — ...

Page 14

... Si4704/05-D60 Table 9. 64–75.9 MHz Input Frequency FM Receiver Characteristics (V = 2 1. Parameter Input Frequency , 4,5,6 8 Sensitivity 3,7 LNA Input Resistance 3,7 LNA Input Capacitance 9 Input IP3 3,4,5,7 AM Suppression Adjacent Channel Selectivity Alternate Channel Selectivity 4,5,7 Audio Output Voltage 4,7,10 ...

Page 15

... Hz—20 kHz SNR kHz at –60 dBFS A-weighted kHz at –60 dBFS non-weighted kHz with 3% Bandpass filter LIATTEN[1: – °C) Test Condition –0.1 dB 20—20 kHz Rev. 1.0 Si4704/05-D60 Min Typ Max Unit — 0.035 0.06 % — 85 — dB — 78 — dB — 90 — dB — ...

Page 16

... ESR CL–single ended Notes: 1. The Si4704/05-D60 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “AN332: Si47xx Programming Guide” frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing. ...

Page 17

... To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface. 6. Place Si4704/05-D60 as close as possible to antenna and keep the FMI traces as short as possible. Optional: Digital Audio Out OPMODE: 0xB0, 0xB5 ...

Page 18

... To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 6. Pin 8 connects to the FM antenna interface. 7. Place Si4704/05-D60 as close as possible to antenna and keep the FMI traces as short as possible ...

Page 19

... Bill of Materials 3.1. QFN/SSOP Bill of Materials Table 13. Si4704/05-D60 QFN/SSOP Bill of Materials Component(s) C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R C2 Coupling capacitor, 1 nF, ±20%, Z5U/X7R C4 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R U1 Si4704/05-D60 FM Radio Tuner C5, C6 Crystal load capacitors, 22 pF, ±5%, COG (Optional for crystal oscillator) C7 Coupling capacitor, 0.39 μ ...

Page 20

... The device supports I Offering control interface, compatible 3-wire control interface. The Si4704/05-D60 utilizes digital signal processing to achieve high fidelity, optimal performance, and design flexibility. The chip provides excellent pilot rejection, selectivity, and unmatched audio performance, and offers both the manufacturer and the end-user extensive programmability and a better listening experience ...

Page 21

... Operating Modes The Si4704/05-D60 operates in either an FM receive or audio AUXIN ADC mode mode, radio signals are received on FMI and processed by the FM front-end circuitry. In audio AUXIN ADC mode, stereo audio signals on LIN/RIN are sampled, converted to digital, filtered, and decimated to 32, 44. kHz for the I digital audio interface ...

Page 22

... Si4704/05-D60 INVERTED (OFALL = 1) DCLK DCLK (OFALL = 0) DFS (OMODE = 0000) 1 DCLK DOUT 1 2 MSB INVERTED (OFALL = 1) DCLK (OFALL = 0) DCLK DFS Left-Justified (OMODE = 0110) DOUT 1 2 MSB Figure 9. Left-Justified Digital Audio Format DCLK (OFALL = 0) DFS DOUT 1 (OMODE = 1100) st (MSB at 1 rising edge) MSB ...

Page 23

... Si4704/05-D60 monitors and provides indicators of the signal quality, allowing the host processor to perform additional processing if required by the customer. The Si4704/05-D60 monitors signal quality metrics including RSSI, SNR, and multipath interference on FM signals. These metrics are used to optimize signal processing and are also reported to the RDS/ host processor ...

Page 24

... The device sets interrupts with found valid stations or, if the seek results in zero found valid stations, the device indicates failure and again sets an interrupt. Refer to “AN332: Si47xx Programming Guide”. The Si4704/05-D60 uses RSSI, SNR, and AFC to 24 qualify stations. programmable thresholds for modifying the seek function according to customer needs ...

Page 25

... D60 and receive responses from the device. The serial port can operate in two bus modes: 2-wire mode and 3- wire mode. The Si4704/05-D60 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal ...

Page 26

... Putting the device in powerdown mode will disable analog and digital circuitry while keeping the bus active. 4.21 Operation (SSOP Only) The Si4704/05-D60 is capable of operating down the battery drains in an application. Any power-up or reset is not guaranteed to work below the dc characteristics defined in Table 3. This capability enables a much longer run time in battery operated devices ...

Page 27

... Pin Descriptions 5.1. Si4704/05-D60-GM RFGND Pin Number(s) Name connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND RF ground. Connect to ground plane on PCB. 4 LPI Embedded antenna input. 5 Device reset input (active low). RST 6 Serial enable input (active low). ...

Page 28

... Si4704/05-D60 5.2. Si4704/05-D60-GU Pin Number(s) Name 1 DOUT/[RIN] Digital output data for digital output mode or Right channel input for AUX IN ADC mode. 2 DFS/[LIN] Digital frame synchronization input for digital output mode or Left channel input for AUXIN ADC mode. 3 GPO3/[DCLK] General purpose output, crystal oscillator, or digital bit synchronous clock input in digital output mode ...

Page 29

... Ordering Guide 1 Part Number Si4704-D60-GM FM Broadcast Radio Receiver 2 Si4704-D60-GU Si4705-D60-GM FM Broadcast Radio Receiver with 2 RDS/RBDS Si4705-D60-GU Notes: 1. Add an “(R)” at the end of the device part number to denote tape and reel option. 2. SSOP devices operate down to V Description = °C. A Rev. 1.0 Si4704/05-D60 ...

Page 30

... Circle = 0.5 mm Diameter Line 3 Marking: (Bottom-Left Justified Year WW = Workweek 30 0560 DTTT YWW 04 = Si4704 Si4705-D60 Firmware Revision 6. Revision D Die. Internal tracking code. Pin 1 Identifier. Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev. 1.0 ...

Page 31

... Mark Method: Part Number Die Revision Line 1 Marking: Firmware Revision Package Type YY = Year WW = Work week Line 2 Marking: TTTTTT = Manufacturing code 470XD60GU YYWWTTTTTT 4704 = Si4704; 4705 = Si4705-D60 Revision D die Firmware Revision 6. 24-pin SSOP Pb-free package Assigned by the Assembly House. Rev. 1.0 Si4704/05-D60 31 ...

Page 32

... Si4704/05-D60 8. Package Outline 8.1. Si4704/05-D60 QFN Figure 12 illustrates the package details for the Si4704/05-D60. Table 15 lists the values for the dimensions shown in the illustration. Figure 12. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 A1 0.00 0.02 b 0.20 0.25 c 0.27 ...

Page 33

... Si4704/05-D60 SSOP Figure 13 illustrates the package details for the Si4704/05-D60. Table 16 lists the values for the dimensions shown in the illustration. Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...

Page 34

... Si4704/05-D60 9. PCB Land Pattern 9.1. Si4704/05-D60 QFN Figure 14 illustrates the PCB land pattern details for the Si4704/05-D60-GM QFN. Table 17 lists the values for the dimensions shown in the illustration. 34 Figure 14. PCB Land Pattern Rev. 1.0 ...

Page 35

... A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Si4704/05-D60 Symbol Millimeters Min GE 2.10 W — ...

Page 36

... Si4704/05-D60 9.2. Si4704/05-D60 SSOP Figure 15 illustrates the PCB land pattern details for the Si4704/05-D60-GU SSOP. Table 18 lists the values for the dimensions shown in the illustration.   Table 18. PCB Land Pattern Dimensions Dimension General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...

Page 37

... Customer Support Site: www.silabs.com  This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA is required for complete access. Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Si4704/05-D60 Rev. 1.0 37 ...

Page 38

... Si4704/05-D60 N : OTES 38 Rev. 1.0 ...

Page 39

... Si4704/05-D60 OCUMENT HANGE IST Revision 0.4 to Revision 1.0 Updated application schematic.  Updated pin descriptions.  Rev. 1.0 ...

Page 40

... Si4704/05-D60 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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