ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 30
ADC1112D125F2/DB,598
Manufacturer Part Number
ADC1112D125F2/DB,598
Description
BOARD EVALUATION FOR ADC1112D125
Manufacturer
NXP Semiconductors
Series
-r
Specifications of ADC1112D125F2/DB,598
Design Resources
ADC1x12D Demo Brd PCB Files
Number Of Adc's
2
Number Of Bits
11
Sampling Rate (per Second)
125M
Data Interface
Serial, LVDS/DDR
Input Range
1 ~ 2 Vpp
Power (typ) @ Conditions
1.23W @ 125MSPS
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
ADC1112D125
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6891
Table 19.
Address
(hex)
0003
0005
0006
0008
0011
0012
0013
0014
0015
0016
0017
0020
0021
0022
Register name
Channel index
Reset and
operating mode
Clock
Internal reference R/W
Output data
standard.
Output clock
Offset
Test pattern 1
Test pattern 2
Test pattern 3
Fast OTR
CMOS output
LVDS DDR O/P 1 R/W
LVDS DDR O/P 2 R/W
Register allocation map
11.6.3 Register allocation map
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
SW_
RST
TESTPAT_USER[2:0]
-
-
-
-
-
-
-
-
-
-
Bit 6
-
-
-
-
-
-
-
-
-
-
RESERVED
RESERVED[2:0]
Bit 5
-
-
-
-
-
-
-
-
RESERVED[5:0]
SE_SEL
LVDS_
CMOS
Bit 4
-
-
-
-
-
-
-
DAVI[1:0]
TESTPAT_USER[10:3]
BIT_BYTE_WISE
Bit definition
INTREF_EN
FASTOTR
DIFF_SE
OUTBUF
DAVINV
Bit 3
DIG_OFFSET[5:0]
-
-
-
DAV_DRV[1:0]
OUTBUS_SWAP
RESERVED
RESERVED
Bit 2
-
-
LVDS_INT_TER[2:0]
FASTOTR_DET[2:0]
TESTPAT_SEL[2:0]
DAVPHASE[2:0]
INTREF[2:0]
DATA_FORMAT[1:0]
CLKDIV
ADCB
Bit 1
DATA_DRV[1:0]
OP_MODE[1:0]
-
DATAI[1:0]
DCS_EN 0000 0001
ADCA
Bit 0
-
Default
(bin)
1111 1111
0000 0000
0000 0000
0000 0000
0000 1110
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 1110
0000 0000
0000 0000