AT32UC3C0512C-ALZR Atmel, AT32UC3C0512C-ALZR Datasheet
AT32UC3C0512C-ALZR
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AT32UC3C0512C-ALZR Summary of contents
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... CAN2A and CAN2B protocol compliant, with high-level mailbox system – Two independent channels, 16 Message Objects per Channel ® Microcontroller ® 32-bit AVR Microcontroller AT32UC3C0512C AT32UC3C1512C AT32UC3C2512C Automotive Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. ...
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One 4-Channel 20-bit Pulse Width Modulation Controller (PWM) – Complementary outputs, with Dead Time Insertion – Output Override and Fault Protection • Two Quadrature Decoders • One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC) – Dual Sample and Hold Capability ...
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Description The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on ...
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... The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers ...
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Overview 2.1 Block diagram Figure 2- 9166BS–AVR-02/11 Block diagram aWire RESET_N TDO JTAG TCK NEXUS TDI INTERFACE TMS CLASS 2+ MEMORY PROTECTION UNIT MCKO OCD MDO[5..0] INSTR MSEO[1..0] INTERFACE EVTI_N EVTO_N VBUS D+ USB D- ...
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... USB Ethernet MAC 10/100 I2S Asynchronous Timers Timer/Counter Channels PWM channels QDEC Frequency Meter Watchdog Timer Power Manager Oscillators 12-bit ADC number of channels 12-bit DAC number of channels Analog Comparators JTAG 9166BS–AVR-02/11 Configuration Summary AT32UC3C0512C 512 KB 64KB 1 123 RMII/MII Crystal Oscillator 0.4-20 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) 0 ...
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... Table 2-1. Feature aWire Max Frequency Package 9166BS–AVR-02/11 Configuration Summary AT32UC3C0512C LQFP144 AT32UC3C AT32UC3C1512C AT32UC3C2512C 1 50 MHz TQFP100 TQFP64/QFN64 7 ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. QFN64/TQFP64 Pinout Note: 9166BS–AVR-02/11 on QFN packages, the exposed pad is unconnected. AT32UC3C Table 3-1 on page 11. 8 ...
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Figure 3-2. TQFP100 Pinout 9166BS–AVR-02/11 AT32UC3C 9 ...
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Figure 3-3. LQFP144 Pinout 9166BS–AVR-02/11 AT32UC3C 10 ...
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Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing TQFP ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PA19 PA20 PA21 PA22 22 22 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN O 14 PB11 43 15 PB12 44 16 PB13 45 17 PB14 46 18 PB15 47 19 PB16 48 20 PB17 49 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PC02 PC03 PC04 PC05 69 57 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PC24 88 98 PC25 89 99 PC26 90 100 PC27 91 101 PC28 92 102 PC29 93 105 PC30 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN O 124 PD15 111 125 PD16 112 126 PD17 113 127 PD18 114 128 PD19 115 129 PD20 116 57 88 130 ...
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Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the ...
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OCD AXS register. For details, see the AVR32UC Techni- cal Reference Manual. Table 3-5. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] 3.2.6 Other Functions The functions listed in pin ...
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Table 3-7. Signal Description List Signal Name Function VDDIN_5 1.8V Voltage Regulator Input VDDIN_33 USB I/O power supply VDDCORE 1.8V Voltage Regulator Output GNDIO1 GNDIO2 I/O Ground GNDIO3 GNDANA Analog Ground GNDCORE Ground of the core GNDPLL Ground of the ...
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Table 3-7. Signal Description List Signal Name Function Analog negative reference connected to ADCVREFN external capacitor MCKO Trace Data Output Clock MDO[5:0] Trace Data Output MSEO[1:0] Trace Frame Control EVTI_N Event In EVTO_N Event Out DATA aWire data DATAOUT aWire ...
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Table 3-7. Signal Description List Signal Name Function SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDWE SDRAM Write Enable EXTINT[8:1] External Interrupt Pins NMI_N = EXTINT[0] Non-Maskable Interrupt Pin General Purpose Input/Output - GPIOA, GPIOB, GPIOC, GPIOD PA[29:19] - PA[16:0] ...
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Table 3-7. Signal Description List Signal Name Function RX_CLK Receive Clock RX_DV Receive Data Valid RX_ER Receive Coding Error SPEED Speed TXD[3:0] Transmit Data TX_CLK Transmit Clock or Reference Clock TX_EN Transmit Enable TX_ER Transmit Coding Error WOL Wake-On-LAN PAD_EVT[15:0] ...
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Table 3-7. Signal Description List Signal Name Function NPCS[3:0] SPI Peripheral Chip Select SCK Clock A0 Channel 0 Line A A1 Channel 1 Line A A2 Channel 2 Line A B0 Channel 0 Line B B1 Channel 1 Line B ...
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Table 3-7. Signal Description List Signal Name Function DP USB Device Port Data + VBUS USB VBUS Monitor and OTG Negociation ID ID Pin of the USB Bus VBOF USB VBUS On/off: bus power control port 3.4 I/O Line Considerations ...
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Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack ...
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Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...
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Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically ...
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Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...
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Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...
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Table 4-3. Reg # 33- ...
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Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...
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EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...
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Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...
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An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...
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Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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Memories 5.1 Embedded Memories • Internal High-Speed Flash (See – 512 Kbytes • Internal High-Speed SRAM, Single-cycle access at full speed (See – 64 Kbytes • Supplementary Internal High-Speed System SRAM (HSB RAM), Single-cycle access at full speed – ...
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... EBI SRAM CS0 EBI SRAM CS2 EBI SRAM CS3 EBI SRAM CS1 /SDRAM CS0 HSB-PB Bridge C HSB-PB Bridge B HSB-PB Bridge A Table 5-2. Part Number AT32UC3C0512C AT32UC3C1512C AT32UC3C2512C 5.3 Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFD0000 0xFFFD1000 9166BS–AVR-02/11 ...
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Table 5-3. Peripheral Address Mapping 0xFFFD1400 0xFFFD1800 0xFFFD1C00 0xFFFD2000 0xFFFD2400 0xFFFD2800 0xFFFD2C00 0xFFFD3000 0xFFFE0000 0xFFFE1000 0xFFFE2000 0xFFFE2400 0xFFFE2800 0xFFFE2C00 0xFFFE3000 0xFFFF0000 0xFFFF0400 0xFFFF0800 0xFFFF0C00 9166BS–AVR-02/11 Universal Synchronous/Asynchronous USART1 Receiver/Transmitter - USART1 SPI0 Serial Peripheral Interface - SPI0 CANIF Control Area ...
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Table 5-3. Peripheral Address Mapping 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF2000 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 9166BS–AVR-02/11 WDT Watchdog Timer - WDT EIC External Interrupt Controller - EIC FREQM Frequency Meter - ...
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Table 5-3. Peripheral Address Mapping 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers ...
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Table 5-4. Port 9166BS–AVR-02/11 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output ...
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Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The AT32UC3C has several types of power supply pins: • VDDIO pins (VDDIO1, VDDIO2, VDDIO3): Power I/O lines. Two voltage ranges are available 3.3V nominal. The VDDIO ...
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Figure 6-1 on page 46 I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO1 = VDDIO2 = VDDIO3 = VDDANA). Figure 6-1. C IN2 6.1.3.2 3.3V Single Supply Mode In 3.3V single supply mode, ...
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Figure 6-2. C IN2 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this ...
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Startup Considerations This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of clocks At power-up, the BOD33 and ...
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Electrical Characteristics 7.1 Absolute Maximum Ratings* Operating temperature................................... -40°C to +125°C Storage temperature...................................... -60°C to +150°C Voltage on any pin except DM/DP/VBUS with respect to ground ............................ -0. Voltage on DM/DP with respect to ground.........-0.3V to +3.6V ...
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Table 7-2. Supply Rise Rates and Order Symbol Parameter V DC supply internal 3.3V regulator VDDIN_5 V DC supply internal 1.8V regulator VDDIN_33 V VDDIO1 V DC supply peripheral I/O VDDIO2 V VDDIO3 DC supply peripheral I/O and V VDDANA ...
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Internal 3.3V regulator is off • 25°C A • I/Os are configured as inputs, with internal pull-up enabled. • Oscillators – OSC0/1 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) stopped – PLL0 running – PLL1 stopped ...
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Figure 7-1. 7.4.1 Peripheral Power Consumption The values in conditions. • Operating conditions core supply – V – V – V – V – Internal 3.3V regulator is off. • 25°C A • I/Os are configured as inputs, ...
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PLL1 stopped • Clocks – External clock on XIN0 as main clock source. – CPU, HSB, and PB clocks undivided Consumption active is the added current consumption when the module clock is turned on and when the module is ...
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I/O Pin Characteristics Table 7-6. Normal I/O Pin Characteristics Symbol Parameter R Pull-up resistance PULLUP R Pull-down resistance PULLDOWN Input low-level V IL voltage Input high-level V IH voltage Output low-level V OL voltage Output high-level V OH voltage ...
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Table 7-6. Normal I/O Pin Characteristics Symbol Parameter (3) t Rise time RISE (3) t Fall time FALL I Input leakage current LEAK C Input capacitance IN Note corresponds to either V VDD on page 11 for details. ...
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Oscillator Characteristics 7.6.1 Oscillator (OSC0 and OSC1) Characteristics 7.6.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN0 or XIN1. Table 7-7. Digital Clock Characteristics Symbol Parameter f ...
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Table 7-8. Crystal Oscillator Characteristics Symbol Parameter f Crystal oscillator frequency OUT C Internal equivalent load capacitance i t Startup time STARTUP Notes: 1. Please refer to the SCIF chapter for details. 7.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics 7.6.2.1 Digital ...
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Phase Lock Loop (PLL0 and PLL1) Characteristics Table 7-11. PLL Characteristics Symbol Parameter f Output frequency VCO f Input frequency IN I Current consumption PLL Startup time, from enabling t the PLL until the PLL is STARTUP locked 7.6.4 ...
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Flash Characteristics Table 7-15 wait states. The FSW bit in the FLASHC FSR register controls the number of wait states used when accessing the flash memory. Table 7-15. Maximum Operating Frequency Flash Wait States 0 1 Table 7-16. Flash ...
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Analog Characteristics 7.8.1 1.8V Voltage Regulator Characteristics Table 7-18. 1.8V Voltage Regulator Electrical Characteristics Symbol Parameter V Input voltage range VDDIN_5 V Output voltage, calibrated value VDDCORE V Output voltage accuracy ACCURACY I DC output current OUT I Static ...
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Brown Out Detector (BOD18) Characteristics The values in Table 7-21. BODLEVEL Value 7.8.4 3.3V Brown Out Detector (BOD33) Characteristics The values in Table 7-23. BOD33.LEVEL Value ...
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Brown Out Detector (BOD50) Characteristics The values in Table 7-25. BOD50.LEVEL Value 9166BS–AVR-02/11 Table 7-25 describe the values of the BOD50.LEVEL field in the SCIF module. BOD50.LEVEL Values Parameter AT32UC3C Min Max ...
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Analog to Digital Converter (ADC) and sample and hold (S/H) Characteristics Table 7-27. ADC and S/H characteristics Symbol Parameter Conditions 12-bit resolution mode, V 10-bit resolution mode, V 8-bit resolution mode, V ADC clock f ADC frequency 12-bit resolution ...
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Table 7-30. ADC Inputs Symbol Parameter V ADC input voltage range ADCINn C Internal Capacitance ONCHIP R Switch resistance ONCHIP Figure 7-3. Table 7-31. ADC Transfer Characteristics 12-bit Resolution Mode Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity ...
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Table 7-32. ADC Transfer Characteristics 10-bit Resolution Mode Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: 1. The measures are done ...
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Table 7-34. ADC and S/H Transfer Characteristics (Continued)12-bit Resolution Mode and S/H gain = 1 Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: 1. The measures are done without any I/O activity on ...
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Table 7-38. DAC Outputs Symbol Parameter Output range C Output capacitance LOAD R Output resitance LOAD Note: 1. DACREF corresponds to the internal or external DAC reference voltage depending on the DACREF settings Figure 7-4. Table 7-39. Transfer Characteristics Symbol ...
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Analog Comparator Characteristics Table 7-40. Analog Comparator Characteristics Symbol Parameter Positive input voltage range Negative input voltage range V Offset OFFSET V Hysteresis HYST t Propagation delay DELAY t Start-up time STARTUP Note: 1. The measures are done without ...
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Timing Characteristics 7.9.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula CONST Where t CPU clock the startup time of the oscillator, stop, deepstop, and static sleep ...
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Figure 7-5. Voltage BOD33 threshold at power-up BOD18 threshold at power-up Internal Reset Time Reset 7.9.2 RESET_N characteristics Table 7-44. RESET_N Clock Waveform Parameters Symbol Parameter t RESET_N minimum pulse length RESET 9166BS–AVR-02/11 Startup and Reset Time Startup Time from ...
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USART in SPI Mode Timing 7.9.3.1 Master mode Figure 7-6. Figure 7-7. Table 7-45. USART in SPI Mode Timing, Master Mode Symbol Parameter USPI0 MISO setup time before SPCK rises USPI1 MISO hold time after SPCK rises USPI2 SPCK ...
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Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: Where the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. ...
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Figure 7-9. Figure 7-10. USART in SPI Slave Mode NPCS Timing USPI12 SPCK, CPOL=0 SPCK, CPOL=1 USPI14 NSS Table 7-46. USART in SPI mode Timing, Slave Mode Symbol Parameter USPI6 SPCK falling to MISO delay USPI7 MOSI setup time before ...
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Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: Where on CPOL and NCPHA. chapter for a description of this clock. Maximum SPI Frequency, Slave Output Mode The maximum SPI slave ...
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Figure 7-12. SPI Master Mode With (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) Table 7-47. SPI Timing, Master Mode Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 ...
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Slave mode Figure 7-13. SPI Slave Mode With (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) Figure 7-14. SPI Slave Mode With (CPOL= NCPHA (CPOL= NCPHA= 1) Figure 7-15. SPCK, CPOL=0 SPCK, CPOL=1 NPCS ...
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Table 7-48. SPI Timing, Slave Mode Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup time before SPCK rises SPI8 MOSI hold time after SPCK rises SPI9 SPCK rising to MISO delay SPI10 MOSI setup time before SPCK ...
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TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more information . Table 7-49. TWI-Bus Timing Requirements Symbol Parameter t TWCK and TWD rise time r t TWCK and TWD fall time f t ...
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JTAG Timing Figure 7-16. JTAG Interface Signals Scan Inputs Scan Outputs (1) Table 7-50. JTAG Timings Symbol Parameter JTAG0 TCK Low Half-period JTAG1 TCK High Half-period JTAG2 TCK Period JTAG3 TDI, TMS Setup before TCK High JTAG4 TDI, TMS ...
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EBI Timings See EBI I/O lines description for more details. Table 7-51. SMC Clock Signal. Symbol Parameter 1/(t ) SMC Controller clock frequency CPSMC Note: 1. The maximum frequency of the SMC interface is the same as the max ...
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Table 7-53. SMC Read Signals with no Hold Settings Symbol Parameter SMC Data setup before NRD high 19 SMC Data hold after NRD high 20 SMC Data setup before NCS high 21 SMC Data hold after NCS high 22 Note: ...
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Table 7-55. SMC Write Signals with No Hold Settings (NWE Controlled only) Symbol Parameter SMC NWE rising to A2-A25 valid 37 SMC NWE rising to NBS0/A0 valid 38 SMC NWE rising to A1/NBS2 change 40 SMC NWE rising to NCS ...
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Figure 7-18. SMC Signals for NRD and NRW Controlled Accesses A2-A25 A0/A1/NBS[3:0] NCS SMC9 NRD SMC19 D0 - D15 NWE Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess ...
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Table 7-57. SDRAM Signal Symbol Parameter SDRAMC SDCKE high before SDCK rising edge 1 SDRAMC SDCKE low after SDCK rising edge 2 SDRAMC SDCKE low before SDCK rising edge 3 SDRAMC SDCKE high after SDCK rising edge 4 SDRAMC ...
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Figure 7-19. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC 1 2 SDCKE SDCS RAS CAS SDWE SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 - DQM3 D0 - D15 Read D0 - D15 to Write 9166BS–AVR-02/11 SDRAMC ...
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MACB Characteristics Table 7-58. Ethernet MAC Signals Symbol Parameter MAC Setup for MDIO from MDC rising 1 MAC Hold for MDIO from MDC rising 2 MAC MDIO toggling from MDC falling 3 Note: 1. These values are based on ...
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Figure 7-20. Ethernet MAC MII Mode MDC MDIO COL CRS TX_CLK TX_ER TX_EN TXD[3:0] RX_CLK RXD[3:0] RX_ER RX_DV 9166BS–AVR-02/11 MAC MAC 1 2 MAC MAC 4 5 MAC MAC 6 7 MAC MAC 11 12 MAC MAC 13 14 MAC ...
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Table 7-60. Ethernet MAC RMII Specific Signals Symbol Parameter MAC TX_EN toggling from TX_CLK rising 21 MAC TXD toggling from TX_CLK rising 22 MAC Setup for RXD from TX_CLK 23 MAC Hold for RXD from TX_CLK 24 MAC Setup for ...
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Mechanical Characteristics 8.1 Thermal Considerations 8.1.1 Thermal Data Table 8-1 Table 8-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC θ JA θ JC 8.1.2 Junction Temperature The average chip-junction temperature ...
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Package Drawings Figure 8-1. QFN-64 package drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 8-2. Device and Package Maximum Weight 200 Table 8-3. Package ...
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Figure 8-2. TQFP-64 package drawing Table 8-5. Device and Package Maximum Weight 300 Table 8-6. Package Characteristics Moisture Sensitivity Level Table 8-7. Package Reference JEDEC Drawing Reference JESD97 Classification 9166BS–AVR-02/11 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 91 ...
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Figure 8-3. TQFP-100 package drawing Table 8-8. Device and Package Maximum Weight 500 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 9166BS–AVR-02/11 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 92 ...
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Figure 8-4. LQFP-144 package drawing Table 8-11. Device and Package Maximum Weight 1300 Table 8-12. Package Characteristics Moisture Sensitivity Level Table 8-13. Package Reference JEDEC Drawing Reference JESD97 Classification 9166BS–AVR-02/11 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 93 ...
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Soldering Profile Table 8-14 Table 8-14. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5⋅C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25⋅C to Peak Temperature ...
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... Ordering Information Table 9-1. Device Ordering Code AT32UC3C0512C-ALZT AT32UC3C0512C AT32UC3C0512C-ALZR AT32UC3C1512C-AZT AT32UC3C1512C AT32UC3C1512C-AZR AT32UC3C2512C-A2ZT AT32UC3C2512C AT32UC3C2512C-A2ZR AT32UC3C2512C-Z2ZT AT32UC3C2512C AT32UC3C2512C-Z2ZR 9166BS–AVR-02/11 Ordering Information Carrier Type Package Tray LQFP 144 Tape & Reel Tray TQFP 100 Tape & Reel Tray TQFP 64 Tape & Reel ...
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Errata 10.1 rev E 10.1.1 AST 1 AST wake signal is released one ast clock cycle after the busy register is cleared After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle ...
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Disabling SPI has no effect on TDRE whereas the write data command is filtered when SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset the TDRE flag by writing in the ...
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USBC 1 UPINRQx.INRQ field is limited to 8-bits In Host mode, when using the UPINRQx.INRQ feature together with the multi-packet mode to launch a finite number of packet among multi-packet, the multi-packet size (located in the descriptor table) is ...
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D 10.2.1 AST 1 AST wake signal is released one ast clock cycle after the busy register is cleared After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle after the ...
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The PLLCOUNT field of the PLL Control Register should always be written to zero. 2 PLL lock might not clear after disable Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator may not go back to ...
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TWIM 1 SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. ...
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Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. B – 02/ ...
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Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 Package and Pinout ................................................................................. 8 4 Processor and Architecture .................................................................. 25 5 Memories ................................................................................................ 41 6 Supply and Startup Considerations ..................................................... 48 7 Electrical Characteristics ...................................................................... 52 8 Mechanical Characteristics ................................................................... ...
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Ordering Information ............................................................................. 76 10 Errata ....................................................................................................... 77 11 Datasheet Revision History .................................................................. 80 9166BS–AVR-02/11 8.1 Thermal Considerations ..................................................................................70 8.2 Package Drawings ...........................................................................................71 8.3 Soldering Profile ..............................................................................................75 10.1 rev D ................................................................................................................77 11.1 Rev. A – 10/10 .................................................................................................80 AT32UC3C 105 ...
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