74LV4051DB,112 NXP Semiconductors, 74LV4051DB,112 Datasheet

IC MUX/DEMUX 8X1 16SSOP

74LV4051DB,112

Manufacturer Part Number
74LV4051DB,112
Description
IC MUX/DEMUX 8X1 16SSOP
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet

Specifications of 74LV4051DB,112

Function
Multiplexer/Demultiplexer
Circuit
1 x 8:1
On-state Resistance
60 Ohm
Current - Supply
80µA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SSOP (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LV4051DB
74LV4051DB
935190980112
1. General description
2. Features
The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with three digital select
inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to
Y7) and a common input/output (Z). It is a low-voltage Si-gate CMOS device that is pin
and function compatible with 74HC4051 and 74HCT4051. With E LOW, one of the eight
switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are
in the high-impedance OFF-state, independent of S0 to S2.
V
The V
can swing between V
exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, V
GND (typically ground).
I
I
I
I
I
I
I
I
CC
74LV4051
8-channel analog multiplexer/demultiplexer
Rev. 04 — 10 August 2009
Optimized for low-voltage applications: 1.0 V to 6.0 V
Accepts TTL input levels between V
Low ON resistance:
Logic level translation:
Typical ‘break before make’ built in
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
N
N
N
N
N
N
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
CC
145
80
60
To enable 3 V logic to communicate with 3 V analog signals
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
to GND ranges are 1.0 V to 6.0 V. The analog inputs/outputs (Y0 to Y7, and Z)
(typical) at V
(typical) at V
(typical) at V
CC
as a positive limit and V
CC
CC
CC
V
V
V
EE
EE
EE
= 3.0 V
= 4.5 V
= 2.0 V
CC
= 2.7 V and V
EE
as a negative limit. V
CC
= 3.6 V
EE
Product data sheet
is connected to
CC
V
EE
may not

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74LV4051DB,112 Summary of contents

Page 1

Rev. 04 — 10 August 2009 1. General description The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LV4051N +125 C 74LV4051D +125 C 74LV4051DB +125 C 74LV4051PW +125 C 74LV4051BQ +125 C 4. Functional diagram Fig 1. Functional diagram 74LV4051_4 Product data sheet Description DIP16 plastic dual in-line package; 16 leads (300 mil) SO16 plastic small outline package ...

Page 3

... NXP Semiconductors Fig 2. Logic symbol from logic Fig 4. Schematic diagram (one switch) 74LV4051_4 Product data sheet 001aad541 Fig 3. Rev. 04 — 10 August 2009 74LV4051 8-channel analog multiplexer/demultiplexer MUX/DMUX 001aad542 IEC logic symbol 001aad544 © NXP B.V. 2009. All rights reserved ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning 74LV4051 GND 001aak433 Fig 5. Pin configuration SOT38-4 and SOT109-1 5.2 Pin description Table 2. Pin description Symbol Pin GND 8 S0, S1, S2 11, 10, 9 Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12 independent input or output 74LV4051_4 Product data sheet ...

Page 5

... NXP Semiconductors 6. Functional description 6.1 Function table [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol Parameter V supply voltage ...

Page 6

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW T ambient temperature amb t/ V input transition rise and fall rate V [1] The static characteristics are guaranteed from V input levels GND Fig 8. ...

Page 7

... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL I input leakage current I I OFF-state leakage current S(OFF) I ON-state leakage current S(ON) I supply current CC I additional supply current ...

Page 8

... NXP Semiconductors 9.1 Test circuits and Fig 9. Test circuit for measuring OFF-state leakage current 9.2 ON resistance Table 7. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 12. Symbol Parameter R ON resistance (peak) ON(peak resistance mismatch ON between channels ...

Page 9

... NXP Semiconductors Table 7. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 12. Symbol Parameter R ON resistance (rail) ON(rail resistance (rail) ON(rail) [1] Typical values are measured at T [2] When supply voltages ( 1 recommended to use these devices only for transmitting digital signals. ...

Page 10

... NXP Semiconductors 9.3 On resistance waveform and test circuit Fig 11. Test circuit for measuring Fig 12. Typical function of input voltage ON 74LV4051_4 Product data sheet GND = V GND 180 2 120 1.2 2.4 Rev. 04 — 10 August 2009 74LV4051 8-channel analog multiplexer/demultiplexer 001aak411 001aak412 3.6 4 ...

Page 11

... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay Yn; see enable time E to Yn, Z; see Yn; see 74LV4051_4 Product data sheet [2] Figure [ [2] Figure ...

Page 12

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t disable time E to Yn, Z; see dis Yn; see power dissipation capacitance V = GND [1] All typical values are measured the same as t and PLH PHL ...

Page 13

... NXP Semiconductors 10.1 Waveforms Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 13. Propagation delay input (An) to output (Yn) Sn, E input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load ...

Page 14

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 15. Test circuit for measuring switching times Table 10. ...

Page 15

... NXP Semiconductors 10.2 Additional dynamic parameters Table 11. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); V specified 6.0 ns amb Symbol Parameter THD total harmonic distortion frequency ( 3dB) response isolation (OFF-state) iso V crosstalk voltage ct Xtalk crosstalk [1] Adjust f voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 50 ). ...

Page 16

... NXP Semiconductors 10.2.1 Test circuits 0.1 F GND = V GND f i Fig 16. Test circuit for measuring frequency response 0.1 F GND = Fig 18. Test circuit for measuring isolation (OFF-state) 74LV4051_4 Product data sheet (dB 001aak420 Fig 17. Typical frequency response (dB 001aak421 Fig 19. Typical isolation (OFF-state) as function of Rev. 04 — 10 August 2009 ...

Page 17

... NXP Semiconductors Fig 20. Test circuit for measuring total harmonic distortion Test circuit b. Input and output pulse definitions V may be connected Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch 74LV4051_4 Product data sheet GND = V EE GND GND = logic off ...

Page 18

... NXP Semiconductors GND a. Switch closed condition GND b. Switch open condition Fig 22. Test circuit for measuring crosstalk between switches 74LV4051_4 Product data sheet 0.1 F GND = Rev. 04 — 10 August 2009 74LV4051 8-channel analog multiplexer/demultiplexer 001aak434 GND = 001aak435 © NXP B.V. 2009. All rights reserved. ...

Page 19

... NXP Semiconductors 11. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 20

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 21

... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 25. Package outline SOT338-1 (SSOP16) ...

Page 22

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 23

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 24

... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type number 74LV4051BQ (DHVQFN16 package) 74LV4051_3 ...

Page 25

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 26

... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics 9.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9.3 On resistance waveform and test circuit ...

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