LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 230
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 9-33. FIFO Without Output Registers, Start of Data Write Cycle
The WrEn signal has to be high to start writing into the FIFO. The Empty and Almost Empty flags are high to begin
and Full and Almost full are low.
When the first data gets written into the FIFO, the Empty flag de-asserts (or goes low), as the FIFO is no longer
empty. In this figure we are assuming that the Almost Empty setting flag setting is 3 (address location 3). So the
Almost Empty flag gets de-asserted when the 3rd address location gets filled.
Now let is assume that we continue to write into the FIFO to fill it. When the FIFO is filled, the Almost Full and Full
Flags are asserted. Figure 9-34 shows the behavior of these flags. In this figure we assume that FIFO depth is ‘N’.
Almost
Almost
Empty
Empty
Reset
Clock
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
9-31
Invalid Q
Data_3
LatticeECP/EC and LatticeXP Devices
Data_4
Data_5
Memory Usage Guide
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