LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 277
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Appendix C. VHDL Example for DDR Input and Output Modules
library IEEE;
use IEEE.std_logic_1164.all;
library ec;
use ec.components.all;
entity ddr_mem is
--*****DDR interface signals assigned SSTL25 IO Standard *************
ATTRIBUTE IO_TYPE
ATTRIBUTE IO_TYPE OF ddrclk
ATTRIBUTE IO_TYPE OF dq
ATTRIBUTE IO_TYPE OF dqs
end ddr_mem;
architecture structure of ddr_mem is
--*****DDR Input register*********************************************
component IDDRXB
end component;
port(
D
ECLK : in STD_LOGIC;
SCLK : in STD_LOGIC;
CE
LSR
DDRCLKPOL
QA
QB
port( dq
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC;
: out STD_LOGIC);
dqs
clk
clk90
reset
uddcntl
read
dataout_p : in std_logic_vector(7 downto 0);
dataout_n : in std_logic_vector(7 downto 0);
datatri_p : in std_logic_vector(7 downto 0);
datatri_n : in std_logic_vector(7 downto 0);
dqstri_p
dqstri_n
ddrclk
datain_p
datain_n
dqsc
prmbdet
lock
ddrclkpol : out std_logic);
: in STD_LOGIC;
: inout std_logic_vector(7 downto 0 );
: inout std_logic;
: in std_logic; -- core clock
: in std_logic; -- 90 degree phase shifted clock from the pll
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic;
: out std_logic_vector(7 downto 0);
: out std_logic_vector(7 downto 0);
: out std_logic;
: out std_logic;
: out std_logic;
: string;
: SIGNAL IS "SSTL25D_II";
: SIGNAL IS "SSTL25_II";
: SIGNAL IS "SSTL25_II";
10-24
LatticeECP/EC and LatticeXP
DDR Usage Guide
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