LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 341
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 12-3. Two SPI Flash
SPIX Mode
Not all SPI memories are the same. A read operation code is required to be fed to the SPI Flash at the time config-
uration starts. For many, that op code is 03 Hex. For other memories that require a different read operation code
other than 03 Hex, the SPIX format is supported. In SPIX mode the read operation code is coded into the SPID[7:0]
pins through the use of pull-ups and pull-downs as shown in Figure 12-4. When configuration begins in the SPIX
mode the SPID[7:0] pins are sampled and the corresponding sampled read operation code will be fed to the SPI
device so the FPGA can begin read back.
All combinations of SPI Flash and LatticeECP/EC FPGAs are valid in the SPIX mode as well. The only addition is
the pull-up and pull-down resistors placed on SPID[7:0] as shown in Figure 12-4.
SPIX Master
Mode
SCK
CS
SI
SCK
CS
SI
CFG[2]
SPI Flash 0
SPI Flash 1
0
SO
SO
CFG[1]
12-8
NC
0
LatticeECP/EC sysCONFIG Usage Guide
CCLK
CSSPIN
SISPI
SPID0
SPID1
SPID[2:7]
PROGRAMN
Lattice FPGA
CFG[0]
1
CFG0
CFG2
CFG1
SPI
SPIX
CONFIG_MODE Parameter
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