LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 411
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
The above information was specified under the following environmental conditions:
The goal of this exercise is to compute the following device I/O constraints:
The only parameter which can be obtained from the above is the device junction temperature:
The required constraints can be computed as follows:
1. Input setup specification
2. Input hold specification
3. Output maximum propagation delay requirement
4. Output minimum propagation delay requirement
5. Output loading
The preference file to use for this example is shown in Figure 17-3. For more preference language syntax and
examples, refer to the Constraints & Preferences section of the ispLEVER on-line help system.
• Board trace AC loading (Cbac): 60 pf.
• Board trace parasitic capacitance (Cb): 5 pf.
• Port controller input capacitance (Cp) :9 pf.
• FPGA device input capacitance (Co): 9 pf.
• Maximum ambient temperature (Ta): 70 (C.
• Estimated Power Consumption (Q): 2 W.
• 680 PBGAM Package Thermal resistance (j) at 0 feet per minute (fpm) airflow: 13.4 °C/W.
1. Input setup specification.
2. Input hold specification.
3. Maximum output propagation delay.
4. Minimum output propagation delay.
5. Output loading.
6. Temperature.
Tj = j * Q - Ta
= 13.4 * 2 + 70
= 96.8 °C
= P - PDMAXp - PDMAXb - Tskew
= 30 - 18 - 2 - 1
= 9 ns
= PDMINp + PDMINb - Tskew
= 3 + 1 - 1
= 3 ns
= P - TSp - PDMAXb - Tskew
= 30 - 5 - 6 - 1
= 18 ns
= Thp - PDMINb + Tskew
= 3 - 1 + 1
= 3 ns
= Cbac + Cb + Cp
= 60 + 5 + 9
= 74 pf
17-5
Lattice Semiconductor FPGA
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