LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 214
LFXP3E-4TN100I
Manufacturer Part Number
LFXP3E-4TN100I
Description
IC FPGA 3.1KLUTS 62I/O 100-TQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP3E-4TN100I
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Part Number:
LFXP3E-4TN100I
Manufacturer:
Lattice Semiconductor Corporation
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Figure 9-58. PFU Based Distributed Dual Port RAM Timing Waveform – With Output Registers
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-59 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-59. Distributed ROM Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. The basic Distributed Dual Port RAM
primitive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-60.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
Reset
Data
WE
Q
t
t
t
SUWREN_PFU
SUWREN_PFU
t
SUADDR_PFU
SUDATA_PFU
Data_0
Add_0
OutClockEn
OutClock
t
t
HADDR_PFU
HDATA_PFU
Address
t
HWREN_PFU
Reset
Invalid Data
Data_1
Add_1
9-49
Distributed ROM
PFU-based
t
SUCE_PFU
Add_0
LatticeECP/EC and LatticeXP Devices
t
HWREN_PFU
t
CORAM_PFU
Q
Data_0
Add_1
Memory Usage Guide
Data_1
t
HCE_PFU
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