LAXP2-17E-5QN208E Lattice, LAXP2-17E-5QN208E Datasheet - Page 36
LAXP2-17E-5QN208E
Manufacturer Part Number
LAXP2-17E-5QN208E
Description
IC FPGA AUTO 17K LUTS 208-PQFP
Manufacturer
Lattice
Datasheet
1.LAXP2-5E-5TN144E.pdf
(83 pages)
Specifications of LAXP2-17E-5QN208E
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 2-31. DQS Local Bus
Polarity Control Logic
In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown. The LA-LatticeXP2 family contains dedicated cir-
cuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between
DQS (delayed) and the system clock, a clock polarity selector is used. This changes the edge on which the data is
registered in the synchronizing registers in the input register block and requires evaluation at the start of each
READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
DQSXFER
DQS
DQS
DCNTL[6:0]
ECLK1
DQSXFER
DCNTL[6:0]
CLK1
GSR
DQS
CEI
2-33
DQSXFERDEL*
Polarity Control
DQSDEL
Logic
PIO
PIO
To DDR
Register Block
Register Block
Reg.
Output
Input
Calibration bus
To Sync
from DLL
LA-LatticeXP2 Family Data Sheet
Reg.
Buffer
Buffer
sysIO
sysIO
DI
DI
Strobe
Datain
DDR
DQS
PAD
PAD
Architecture
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