LFE2-50E-6FN484C Lattice, LFE2-50E-6FN484C Datasheet - Page 20
LFE2-50E-6FN484C
Manufacturer Part Number
LFE2-50E-6FN484C
Description
IC FPGA 50KLUTS 339I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-50E-6FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Slice Clock Selection
Figure 2-17 shows the clock selections and Figure 2-18 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals can be used
as a clock input to the slices via routing. Slice controls are generated from the secondary clocks or other signals
connected via routing.
If none of the signals are selected for both clock and control then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Figure 2-17. Slice0 through Slice2 Clock Selection
Figure 2-18. Slice0 through Slice2 Control Selection
Edge Clock Routing
LatticeECP2/M devices have a number of high-speed edge clocks that are intended for use with the PIOs in the
implementation of high-speed interfaces. There are eight edge clocks per device: two edge clocks per edge. Differ-
ent PLL and DLL outputs are routed to the two muxes on the left and right sides of the device. In addition, the
CLKO signal (generated from the DLLDELA block) is routed to all the edge clock muxes on the left and right sides
of the device. Figure 2-19 shows the selection muxes for these clocks.
Secondary Clock
Secondary Clock
Primary Clock
Routing
Routing
Vcc
Vcc
12
12
8
4
1
3
1
2-17
25:1
16:1
LatticeECP2/M Family Data Sheet
Clock to Slice
Slice Control
Architecture
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